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Recent content by soloktanjung

  1. S

    Mixed signal design - flow and price

    Hi, I know about mixed signal design flow using either cadence or synopsys tools. But I am not clear with the technology used to design the analog parts. Let say, I design my digital blocks using 130nm, then how can I ensure that the analog parts will be according to 130nm technology? Does the...
  2. S

    serdes vs transceiver

    Hi, I need some clarification regarding serdes and transceiver. I know what serdes is and i just read xilinx user guide on transceiver (7series transceiver user guide) and did not understand clearly. Is serdes functionality is a part of the MGT (multigigabit transceiver) or is it a different...
  3. S

    ASIC design evalution tools

    Thanks for the link. Nice to know that. Thanks again.
  4. S

    ASIC design evalution tools

    There are no free tools for ASIC design for synthesis and place and route to my knowledge. Have you tried to contact the companies (synopsys, cadence, etc) discussing about the evaluation/demo version? Link: **broken link removed** Send an email to them and see what they reply. Thanks
  5. S

    State Machine issues! Output and Testbench!

    The testbench to test the FSM is just driving a value to all the inputs in the FSM design (your entity ports) according to all sequence of transitions as in the state machine diagram. that's all.
  6. S

    static timing analaysis

    Agree. Search in this forum, you will find many related threads.
  7. S

    Core utilization improvement

    Reduce the height and width of your core area so that initial core utilization increase to about 60% (i think 60% utilization is a good start). Later when you perform CTS and routing, it will increase the core utilization (perhaps until 80%) because the tool will add many repeaters to your design.
  8. S

    Architecture and Micro-Architecture?

    Hi, I think micro-architecture is just to show about the very internal and small architectures of a large architecture.
  9. S

    explain carry skip adder

    Hi, Page 8 in this doc: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/L2_Notes.pdf
  10. S

    STA by primetime and violation

    Hi, I know about fix_eco_timing but have not tried it yet. Maybe you can consider it. Link: https://www.edaboard.com/threads/221222/ https://www.edaboard.com/threads/248811/
  11. S

    Divider being infered by DC doesn't work?

    Yes I agree. the problem might be not in the code you have posted. Please post a complete code to track the problem.
  12. S

    State Machine issues! Output and Testbench!

    I agree. From the state diagram, I do not see any outputs.
  13. S

    please help me to fix my translation from VHDL to Verilog

    Hi, I think,one way to check it is by simulating the VHDL code and then compared with the output of translated Verilog using the same testbench architecture. Thanks
  14. S

    VHDL memory design using registers for spartan 3

    Hi, From google: http://quartushelp.altera.com/12.1/mergedProjects/hdl/vhdl/vhdl_pro_registers.htm
  15. S

    To understand Makefiles what language we should know ?

    Hi, I dont think the Makefile is related to other programming language. You can understand and write your own Makefile without knowing any programming language. Thanks.
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