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the most radical thing to do is to change the actual project. find out which is the longest path, try to find the reason why it is the longest one and try to simplify it.
if your project is somewhat academic and it wont get fab, just change the input delay to a negative number. this will fix...
the first solution pointed out by qieda works. yet, i really couldnt understand what you were actually trying to do. please ttry to explain better what u are trying to do, perhaps a better solution exists.
i have had problems in the past using encounter to verify drc and antennas. the tool reported several false errors. if possible use some virtuoso integrated tool.
these delays you mentioned are project specific and should be calculated. they are not supposed to be changed in order to accommodate for any slack value.
have you tried asking the tool to perform synthesis using a high effort? have you tried to give timing a higher importance regarding area or...
gosh...
the functional description is the verilog language! find a good book and you will find out what the nand, buf, or, etc. means.
---------- Post added at 16:34 ---------- Previous post was at 16:29 ----------
search for verilog primitives and you will understand what i am talking about.
I have contacted synopsys support and the problem lies in the file. It does not contain all the info ic compiler needs to start the flow
(although the console messages are not that descriptive that is what actually happened)
to use this library u would have to start the flow using another plib...
Hey all
I am using ic compiler for the first time so i dont know if I am doing something wrong or if my plib file is erroneous. This is what happens when I try to create a library using my plib file:
icc_shell> create_mw_lib -plib ../CORX90GPSVT.plib newlib
Wrote the 'CORX90GPSVT' library to...
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