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others clause is not synthesized
Hi all guys:
I want ro generate a safe state machine, When the machine enter an unexpected state or an unreachable state, it can recove from these error state and run continuely. I have created a finite state machine by VHDL, synthesized by...
dcfifo problem first datas
Hi, all guys
Using the development tool provided by Altera, I generated a LPM DCFIFO as VHDL,whose depth is 128 and whose width is 16bits. Then I instantiated this DCFIFO in a top-level VHDL file, and there is only this one DCFIFO component in this top-level VHDL...
Hi.everyone
I have discribed a VHDL module. But when syhthesizing it by XST, there is a clock warning as follows:
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |...
hi all:
An freqence signal want to be multiplied by FPGA. The input signal is(141K,817K), and the output frequence should be 32 * (141,817) or 128 *(141,817). Besides, DLL in virtex4 are required not to be used.
Dose someone has good ideas?
Any help would be appreciate!
skycanny
Thank for all your replies
Late I found that I did not sepcify the correct path of Simulator when compling the libraries in ISE. Then I sepcified the proper path and repeated the process and this time it worked well. In the end. the libraries were compiled very well and ISE can work together...
ise generate simprim
I install ise6.2 and modelsim SE 6.0 and verify that they are able to work respectively as well as work well together when behavioral function simulating.
However, there is a problem when ise and modelsim work together to make post
simulation. Modelsim gives a hint as "#...
vhdl absolute value
hi, all guys:
In my project, I have to implement an absolute value. I use "abs" of VHDL in my project as "a <= abs(b);",where a and b have the same type, but it dose not work and the following is the error hint:
abs can not have such operands in this context...
Hi, all guys:
I use Modelsim to simulate my project. There are many data in the simlation graphics and I wanna save these many data as text mode such as *.txt file. Cloud this be implemented?
Any help would be appreciate!
Re: Modelsim problem
Hi,kapil:
I do not use any coregen module. And if so, behavioral simulation can not be done before compiling Xilinx Corelib. However,behavioral simulation have been done successfully. So, there must be other reasons. Could someone help me to solve this problem...
Hi, all guys:
I use ISE and Modelsim to develop FPGA. I have described a VHDL module and maded pre-simulation(behavioral simulation) by calling Modelsim in ISE , the pre-simulation result is corrsponding to my expectation. However when I call Modelsim to do post-place and route simulation...
vhdl code rom
hi,Renjith:
You are right
I am trying to implement a DDS and using Xilinx FPGA.
However, I do not want to use CoreGen because the module CoreGen creates is hard to migrate to other target device.
Could you help me?
Any help would be appreciate!
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