Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

safe state machine problem

Status
Not open for further replies.

skycanny

Junior Member level 3
Joined
Dec 23, 2004
Messages
30
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
363
others clause is not synthesized

Hi all guys:
I want ro generate a safe state machine, When the machine enter an unexpected state or an unreachable state, it can recove from these error state and run continuely. I have created a finite state machine by VHDL, synthesized by synplify with the atrribute "safe", however, the log warns that "OTHERS clause is not synthesized", and the synthesed result is tha same as the one sythsized without the attribute "safe". Whenever I add the attribute "safe" in the *.sdc file or directly in the VHDL source file, syplify shows the warning mentioned above. I refer **broken link removed** as my guide, but get this result.
what is wrong? how can I get a safe state machine synthesized by synplify?
Best regard.
 

safe state machines

The safe behaviour is not necessarily corresponding to the existence of an OTHERS state to my opinion. When the OTHERS state is recognized as unreachable by the FSM compiler, it's probably eliminated as with any other FSM style. But due to the safe opion, transitions from illegal states to the reset state should be implemented. You can try by simulation.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top