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Recent content by siddharth1501

  1. S

    power management project

    hi all i am going to start my project on high voltage cmos devices.can anyone help me what extra precautions should i take care in layout
  2. S

    why ESD voltage can apply to pad?voltage difference?

    hi gksivas how it affect the actual logic
  3. S

    INTERNATIONAL ESD STANDARDS

    HI ALL WHAT IS INTERNATIONAL STANDARD ESD CURRENT & FOR HOW MUCH TIME?
  4. S

    WHY CDM NEAR TO XTOR WHY NOT FAR

    hello everyone presently i am doing layout. i heard the CDM SHOULD BE NEAR TO TRANSISTOR.Can anyone help me regarding this? regards siddu.
  5. S

    voltage nets and current nets

    hi all what precautions we should take while routing voltage nets and current nets? regards siddu
  6. S

    order of lvs checking

    hi sandeep i am using caliber. this question is asked in an interview for me.
  7. S

    antenna violation effect- when to use jumper and when diode?

    hi gkvikas you will get lvs error. u have to update ur spice for extra added diode.and drc u have to clean u will get mostly spacing violation.
  8. S

    order of lvs checking

    hi can anyone help me .how the verification is done that is the order of lvs.how is checks like first device or component .....
  9. S

    during fabrication why poly(gate) is manufacture first?

    hi erikl i have seen ur pdf its good n useful n it also in detali.but it still not clear for me. can u refer me how can i clearly understand.
  10. S

    during fabrication why poly(gate) is manufacture first?

    ok keith thanks alot for ur reply.may i know wat is the order of fabrication like first poly gate and next ......
  11. S

    during fabrication why poly(gate) is manufacture first?

    fabrication hi all during fabrication why poly(gate) is manufacture first?
  12. S

    What is the reason for using thick oxide?

    why we use thick oxide? only for breakdown protection or any other reason?
  13. S

    How to construct both pmos and nmos in a single substrate?

    Re: single substrate thats what actually i dint understand how its possible?thats y i put here this question.i have seen this question in intel interview question?its like this "# How can you construct both PMOS and NMOS on a single substrate?" regards siddu
  14. S

    How to construct both pmos and nmos in a single substrate?

    hi all how can i construct both pmos and nmos in a single substrate?
  15. S

    What exactly is the difference between the resistors?

    so u mean functionality is same for both...........ok thanks for ur help
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