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Hi everyone,
This is my first time designing an op amp, using 180nm in Cadence. Two stage design, 1st stage is NMOS differential pair with PMOS current mirror load, second stage is PMOS CS with Miller capacitor. Pictures attached are the DC operating points of the circuit, open loop gain, the...
Not a homework problem, I'm refreshing before semester starts. Problem is from chapter 7 of Razavi Fundamentals. Given are Vth = 0.4V, un*Cox = 200uA/V^2, up*Cox = 100uA/V^2.
Part a I figured out, Av = gm1 * (ro1//ro2), and ro1 and ro2 are 1/(lamba * Id). That gets me gm1, and I set gm1 =...
Oh gosh that makes so much sense. My thoughts went to the CS stage with a resistor between the drain and Vdd, where an increase in Id means a decrease in Vd. Thanks everyone!
This example in Razavi's Microelectronics book seems to break KCL to me. If I_in goes up, by KCL it must increase the Id of M2 right? So Vx will go down, and Vout goes up, and Id of M1 goes down as well, which makes sense because Vx went down.
But what the text states is I_in goes up and Id of...
I'm having a very difficult time understanding what you've written, my apologies I assume English is not your first language.
For your first question, if I understand, you're asking how a DC and AC source can be added like the book shows. That happens because of the capacitor. Capacitors block...
Sorry, wasn't clear enough, this is using the Evaluation board. Schematic and layout for it can be found here: https://www.st.com/resource/en/user_manual/dm00039084-discovery-kit-with-stm32f407vg-mcu-stmicroelectronics.pdf
I'm making the fairly safe assumption that the layout is okay on the...
I've been grappling with the SPI bus for weeks on end to no avail. I've made my own libraries for UART, ADC, Timer etc successfully, so I'm fairly certain it's not any of the common pitfalls like not enabling the clock or misconfiguring the GPIO. I decided to cave and use the HAL libraries...
Sorry, no other parameters are specified. ro is infinite, no parasitics, and gm is to be used as a constant variable. Those don't really matter either way. I know how to derive the expression of the total transfer function given the circuit info, that's not the issue.
I guess this is more of a...
I'm trying to derive an expression for the magnitude of Vout/Vin for this circuit from Razavi. I know that Vout/Vin = (Vx/Vin) * (Vout/Vx), but does the same apply to the magnitude? Can I derive an expression for the magnitude of gain for each stage and multiply together such that |Vout/Vin| =...
Ah sorry didn't properly link it. The cable used to configure the device is this but with a different mating connector: https://ftdichip.com/products/ttl-232r-3v3/
That's about it, there's nothing else to show. It's a GPIO pin used for UART Tx connected to a header that sometimes might be...
Relevant part is attached, can't post the full schematic. The cable used to connect with the port is one of these, but with a different mating connector for the header I linked earlier up. As far as layout goes, there's no vias nearby, and the trace doesn't run within even 20mils of another...
There's no ESD protection on the board for that line. The pin is connected straight to one of these headers and nothing else: https://www.digikey.com/en/products/detail/te-connectivity-amp-connectors/640456-4/109006?s=N4IgTCBcDaIIIEYCcYwFoByAREBdAvkA
Is it recommended to put a 10k series...
I feel like if it were an ESD issue, we would see it happen more often here at the office, and see it with more than just that specific pin. I configure devices hundreds of times throughout testing, often walking around a carpeted office, plugging and unplugging the cable over and over...
I've got an odd problem here. I have this board with an MSP430F5435, and pins 39 and 40 are being used for UART communication, going to a port used for configuration through a PC app. The port is 4 pins, Rx, Tx, GND, Vcc. Pin 40 is the Rx line, pulled up to Vcc by a 100k resistor. Pin 39 is Tx...
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