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Recent content by shivu90

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    Multiple scopes while sdf back annotation

    Hi, If a module is instantiated in multiple hierarchies(x1:dut, x2:dut, x3:dut, ....), how do we specify these scopes while running with SDF in NCSIM.I tried using wildcharacters but it doesnt seem to recognize it. SCOPE = x*:dut Please help. Thanks
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    how to include compiled libraries in Ncsim

    I have few packages (a,b,c) compiled under a library x i.e a file inca.linux86.pak under directory "x" I provide the following in cds.lib : DEFINE x <path to x> and try to compile a design which has the following :- library x use x.a.all use x.b.all when I try to compile the design using :-...
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    Error while dumping multiple vcd files

    Hey, I am trying to dump vcd for each subdesign in my design. Following is my modesim scipt: foreach mod_name [list LFSR tx_buf encoder ldpc_buffer mem_block ] { vcd files out_vcd/$mod_name.vcd vcd add -r /loop_tb/dut_tx/$mod_name/* -file out_vcd/$mod_name.vcd } run 10us vcd flush...
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    What factors do min, max delay values in SDF depend on

    What factors do min, typ and max values of a IOPATH delay depend on. What is it if only one operating condition is specified while generating SDF ? Is it the min max value that delay can take considering various load capacitance's and input slew values? Does it consider the effects of process...
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    How to characterize internal power for a cell using Spice

    Hey, I am trying to re-characterize internal power for some cells in NanGate library using spice simulations. I am not getting the same values. I also tried regenerating the .lib using ELC, cadence's library characterizing tool. But got different results from this too. Does anybody know what...
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    [SOLVED] How to simulate the same verilog for different sdf files in modelSim

    Thanks. i was able to get through. there was a $finish in my test-bench
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    [SOLVED] How to simulate the same verilog for different sdf files in modelSim

    Hey rca, thanks for your reply. But I am unable to generate multiple vcd files. the code that i am using is this:- foreach sdf_file $list_sdf { vsim -sdftyp dut=./sdf/$sdf_file.sdf boothmult_tb vcd file $sdf_file.vcd } run 5000ns and my testbench has $dumpvars(0, boothmult_tb); it...
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    [SOLVED] How to simulate the same verilog for different sdf files in modelSim

    Hey, I am trying to dump vcd's for simulations of a verilog testbench with 100 SDF files. The problem is invoking the tool again and again and reading the design is redundant. The restart command in modelsim only resets the simulation time; i want to compile a different SDF but the rtl is...
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    Specifying minimum number of flops for a scan chain

    While doing scan insertion using RC ... can we give a constraint saying a scan chain should have minimum 3/4 flops ? Is there a way of doing this ? Plz help ... using RC for the first tym
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    Need help with DFT basics

    Thanks for the doc... I am looking for something elaborate which explains in detail to a first timer .. if you have some book like that .. plz guide[COLOR="Silver"]
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    Need help with DFT basics

    Hey I am a Btech fresher.. just joined as DFT engineer ... Can anyone provide a link to some good ebook with which I can get started.. Thanks

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