[SOLVED] How to simulate the same verilog for different sdf files in modelSim

[shivu90]

Hey,

I am trying to dump vcd's for simulations of a verilog testbench with 100 SDF files. The problem is invoking the tool again and again and reading the design is redundant.
The restart command in modelsim only resets the simulation time; i want to compile a different SDF but the rtl is same. Can anybody please help me with this.

Thanks in advance

 

[rca]

well script your simulation to used the 100 sdf, like:
foreach sdf_file $list_100_sdf {
setenv SDF_FILE $sdf_fil; # to used the sdf file name for differentiate the vcd, in the dump_vcd.do script
# do your simulation
vsim -sdfmax $sdf... -do dump_vcd.do;
}

 

[shivu90]

Hey rca,

thanks for your reply.

But I am unable to generate multiple vcd files. the code that i am using is this:-

foreach sdf_file $list_sdf {
vsim -sdftyp dut=./sdf/$sdf_file.sdf boothmult_tb
vcd file $sdf_file.vcd
}
run 5000ns

and my testbench has
$dumpvars(0, boothmult_tb);

it generates empty vcd files

Can u please help me with this. Thanks in advance

 

[rca]

you could used the "-do " with a script which contain the run and vcd creation.

 

[shivu90]

Thanks. i was able to get through.

there was a $finish in my test-bench