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Hi Erikl,
Thanks for your reply and the reference. I check the comment and thinks W and L variation with different corner besides short channel effects may be the factor but they are not so crucial for the discrepancy between different corner simulations with same overdrive voltage since...
hi all,
I am doing the design of constant current LNA independent of the process. Its structure is the common source topology and the drain voltage is fixed to 1 V while gate voltage varies with different process. But the overdrive voltage Vod=Vgs-Vth is nearly fixed for all process. In the...
Dear all,
I am doing the matching work for differential LNA around 2GHz. To save the chip area, the input matching network is depended on the off-chip components, such as inductor and capacitor. But one thing makes me confused: since there will be discrepancies between off-chip components...
Morning, everyone:
I have met a problem in inductor using o.18um cmos simulated by Momentum:
the substrate setting is depicted as follows:
M6(metal)------------- M6
Imd5(substrate)---------- via 5
M5(metal)------------- M5
imd4(substrate)----------via 4
M4(metal)-------------...
nmos2vdnw
Good afternoon:
I have met a problem in the process of running assura RCX extraction. that is shown in the following. Could you help me to solve it?Thanks!
Assura (tm) Physical Verification Version av3.1:Production:dfII5.1.41
Release 3.1.5
Copyright (c) Cadence...
Re: inductor dismatch in lvs
thanks to rfeda. All inductor are picked from the schematic and I have checked the recognition layer is generated in the layout. I guess the problem is not caused by the case of no generated recognition layer. And I change the inductor turn.When the ture is larger...
lvs inductor
I also meet a strange problem in lvs: all parameters on schematic and layout are same but after lvs the inductor parameter of inner radius became zero in layout (dismatch information)while the actual parameter was still no changed.Anyone can help me?Thanks!!
I also meet the same problem in lvs: all parameters on schematic and layout are same but after lvs the inductor parameter of inner radius became zero in layout (dismatch information)while the actual parameter was still no changed.Anyone can help us?Thanks!!
hi,my name is shhaha.I'm a freshman using the HFSS for design.Now i nees your help for a problem when i use HFSS to simulate on-chip symmetric inductor.The chip has 6 layers and 5 metal layers,and the inductor is only fabricated on the top metal and vicinity metal layer.The excitement port is...
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