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Hi all,
I'm trying to generate a "Name Mapping File" for primetime px, starting from a sldb description of "DW_ram_rw_s_dff.v". For normal design with verilog source I don't have any problems but if I use a sldb description (dw_foundation.sldb), design compiler generate an empty "Name Mapping...
That was the problem! Thanks!!! :-D
set search_path {. ../src/hdl/rtl ../../90nm/snps}
set target_library {saed90nm_typ.db}
set synthetic_library {dw_foundation.sldb}
set link_library "$target_library"
set link_library [concat $link_library $synthetic_library]
read_verilog...
I tried to use the "DW_ram_rw_s_dff.v" component that I have found in "/synopsys/synthesis/H-2013.03-SP5-3/dw/sim_ver" but I have the same problem. :bang:
#set search_path {. ../src/hdl/rtl ../src/lib/snps ../src/sim}
#set link_library {* core_typ.db}
#set target_library {core_typ.db}
set...
Hi all,
I'm trying to synthesize the "DW_ram_rw_s_dff" from dw Block IP but I have this warning:
Warning: Cannot find the design 'DW_ram_rw_s_dff' in the library 'WORK'. (LBR-1)
I used the "**broken link removed**" provided by Synopsys. This is my script:
set search_path {. ../src/hdl/rtl...
Hi all,
I'm a student of the University of Verona and for my Master thesis I need to create a cycle-accurate vcd trace of my component, so after various searches on google I found PrimeTime PX (
I don't know if there are better tools, if you know another, can you suggest me?). I searched a...
I send a single character at a time and fpga receives the corrisponding ascii code. When I send a special character ('!' choose by me) the fpga compact the previous characters into a string.
mmm, ok...
I have this problem: I receive a string from uart and I need to convert it to integer to make an operation. My problem is the conversion from string to int.
Can you help?
Hi all,
I want to convert a strings into integer values.
eg: "123" => 123
Can someone recommend a "best" way of converting strings to integers in VHDL?
Thanks
Hi Pete,
I found that the problem is the clock. I use AB13 pin and I have seen at page 28 of "Hardware user guide" that this one is a X2 27MHz OSC so I set in the code: CLOCK_FREQUENCY:positive := 27000000; and now it'is working!!!
I don't know how to use the U6 200MHZ OSC in order to set...
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