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Re: metastability
when all the I/P constraints for a flop such as setup & hold time are meet, then FF produces faithful O/P. However when any one of these constraints is not meet then O/P gets into metastable state which we also call as unstable state (undefined state) from there it may achieve...
Re: what is the mos?
MOS is Metal Oxide Semiconductor transsistor which offers different resistance in different modes of its operation, In digital ckt's it is used as a Switch which turns ON/OFF on the applicatiaon of voltage on its I/P terminals while in analog & mixed signal designs it can...
Re: Unit cell area
Since the cell width & height is in micro-meter i.e. 10e-6
So area calculated will be W*H which will yield um*um = (um)^2 i.e. square microns
Same thing applies to all other geometries
Re: ROM books
hi
Digital Integrated Circuits (2nd Edition) (Printice Hall Electronics and Vlsi Series) by Jan M. Rabaey is a good book if you want to learn about design basics
CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition) by Neil Weste and David Harris is a new book &...
hi
you can create an account in Synopsys Solvenet using your companies email-id its for free & then down load milkyway data preparation doc'n it contains all the steps to create milkyway database.
I've some stuff but I'm on a location where I can't access it, I'd obtained it from solvenet...
ic cell library
Std cell libraries are the basic building block of any advance digital IC, they contain all the combinational & sequential digital & mixed signal cells which will be used for the creation of SOC or ASIC. These cells will be arranged & connected in an orderly & meaning ful...
Re: A question about Library
Artisan is taken over by ARM & is th e leading I would say No-1 in Std cell library dev. Other Std cell developers are Virage logic, I've heard of some European company known as Dolphin I'm not sure though, however so many big giants in industry such as Intel, TI...
Re: Commercial routing tools
Earlier Synopsys had Astro as their PNR tool, but now they've launched IC Compiler for their 65nm process & beyond ICC uses Zroute as its router engine which is a multi-threaded router, belive me life in 45nm is not easy & ICC have shown very good routing results as...
Re: FloorPlan
Floorplanning: Arrange the blocks of the netlist on the chip. In floorplanning we estimate sizes and set the initial relative locations of the various blocks for our soc.
The goal of FP is to calculate the sizes of all the blocks and assign them locations (x-y co-ordinates).
The...
Simulation & verification both uses differential equations to get the response of system by applying i/p test stimulus
In VLSI Simulations are of type arhitectural, behavioural, gate-level, switch level, transistor level etc. in these simulation we try to get the systems response for desired...
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