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Recent content by shaiko

  1. S

    Aligning ones to LSBs

    Can you post how you'd calculate it with a loop ?
  2. S

    Aligning ones to LSBs

    (After searching...)Actually there is. but it does require to be able to count the number of ones (which means another custom function). function align_ones_lsb ( data : std_logic_vector ) return std_logic_vector is variable aligned_ones : std_logic_vector ( data '...
  3. S

    Aligning ones to LSBs

    Hi, I'm looking for an algebraic solution to align the '1' bits of a vector to the LSB's. For example: 11001001 will transform to: 00001111 1000 will transform to: 0001 1100 will transform to 0011. I wrote a custom HDL function that achieves the goal but it's quite complex and will probably...
  4. S

    Assigning to a parameterized 2d Verilog array

    I can, but I'm looking for a single liner - like VHDL's : some_array <= ( others => ( others => '1' ) ) ;
  5. S

    Assigning to a parameterized 2d Verilog array

    Hello, I have a Verilog array defined as : logic [0:num_elements-1] [element_width] some_array ; I want to assign every array element with a vector that is all ones: "11...1". I tried this but I get an error: some_array <= { num_elements { element_width { 1'b1 } } } ; What's the correct syntax ?
  6. S

    Systemverilog One Hot to Binary function

    vGoodtimes, Can you please post an example ?
  7. S

    Looping over a 3d Systemverilog array

    Thanks dave_59. What if my loop was defined as : logic [1:0] [2:0] some_3d_array [3:0] ; // one unpacked dimension How would the code change ?
  8. S

    Looping over a 3d Systemverilog array

    Hello, I have a 3d array defined as : logic [1:0] [2:0] [3:0] some_3d_array ; I want to write a "foreach" loop that iterates over all dimensions. Is this the correct syntax ? foreach (some_3d_array[i]) begin foreach (some_3d_array[i][j]) begin foreach (some_3d_array[i][j][k])...
  9. S

    Systemverilog One Hot to Binary function

    Can you please post an example ?
  10. S

    ZYNQ based data acquisition system

    Is this a source synchronous interface ? I.E: does the ADC transmit a clock together with the data ? Provide a link to the ADC datasheet.
  11. S

    Systemverilog function output vs returned value

    Thanks dave_59. But isn't the scope of "element" local to the function? How do we get the value of "element" outside of the function. For example: suppose we have a signal named: "some_signal". What's the syntax to assign it the value of "element" ?
  12. S

    Systemverilog One Hot to Binary function

    Hello, My design requires converting a One Hot encoded vector to Binary from. For this purpose - I want to write a generic function that can accept any size of vector. My problem is that Systemverilog doesn't allow the function to have an unconstrained array input. How can I solve this ...
  13. S

    Systemverilog function output vs returned value

    Hello, I came across this Systemverilog code online: function mul (input int x, y, output int z); z = x*y + 1; return x * y; endfunction As you can see - it outputs the integer 'z' and at the same time returns x*y. Questions: 1.How can we call the function to get the value of 'z' ? 2.What's the...
  14. S

    Reasons behind limitations of unpacked arrays in Systemverilog

    Hello, Systemverilog unpacked arrays have quite a few limitations compared to packed arrays. I especially don't understand why they weren't made to support arithmetic operations. What's the driving motivation behind the limitations ?
  15. S

    Systemverilog "math_real" equivalent

    Thanks dave_59, Can the trigonometric functions be used in synthesis (during compile time) to setup values for constants ?

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