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Systemverilog function output vs returned value

shaiko

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Hello,
I came across this Systemverilog code online:
Code:
function mul (input int x, y, output int z);
z = x*y + 1;
return x * y;
endfunction
As you can see - it outputs the integer 'z' and at the same time returns x*y.
Questions:
1.How can we call the function to get the value of 'z' ?
2.What's the purpose/use case of having an output and a return value.
 

FvM

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System verilog functions can have output and inout arguments as they are used for tasks. They can have zero, one or multiple output values, with various purposes.

You get the value by using a variable as actual argument.
 

    shaiko

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dave_59

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SystemVerilog makes a distinction between subroutines that may consume time (tasks) and those that must not (functions). If you want to use a subroutine as part of an expression, you must use a non-time consuming function that returns a single value. If you have a subroutine that guarantees it won't consume time, use a function.

Tasks are called like a statement and do not return a value. You can use output arguments to pass out values since unlike C/C++, there are no pointers that you could pass in as a reference. (although class handles as an argument work like a passed reference).

Sometimes you need a function to output more than one value. Here the function returns a status indicating success or failure. This leaves the output arugment element free to return any value.

Code Verilog - [expand]
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int AA[string];
int arg;
 
function bit lookup(input string key, output int element);
  if (AA.exists(key) ) begin
        element = AA[key[;
       return 1;
  else return 0;
endfunction
...
if (lookup("mode", arg))
    $display("Found mode : %d", arg)l
else
   $error("Didn't find 'mode');

 

    shaiko

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shaiko

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Thanks dave_59.
But isn't the scope of "element" local to the function?
How do we get the value of "element" outside of the function.
For example:
suppose we have a signal named: "some_signal". What's the syntax to assign it the value of "element" ?
 

dave_59

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Change arg to some_signal in my example.

This a very basic part of Verilog. It's all explained in section 13.5 Subroutine calls and argument passing in the IEEE 1800-2017 LRM, and in many online examples
 
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    shaiko

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