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Hi,
Among the most common async clocks data interface designs is the gray pointer FIFO designs.
Commonly the FIFO is an array of sequential cells at the transmit side.
Also common is to implement this array using edge triggered DFF (unless your design is latch based...).
Why not use level...
Thanks fellas, but you took it to the wrong direction.
I was really asking about fall-2-rise uncertainty vs. rise-2-rise uncertainty. I want to define the fall-2-rise uncertainty requirement to be half of the rise-2-rise uncertainty requirement.
By default the timing tool will use the...
Hi,
For synthesis I use 5% guard on the clock period (setting 95% of nominal period) and also 5% setup uncertainty to cover for clock waveform impurities (jitter etc.).
My design has some fall-rise timing paths which, for these, I feel this 5% uncertainty is a little overhead.
I am considering...
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