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Recent content by shahal

  1. S

    solution manual:Fundamentals of Electromagnetics with MATLAB

    Hi I am looking for solution manual to "Fundamentals of Applied Electromagnetics" 5th edition. Would really appreciate it if some one has it.
  2. S

    what is meant by virtual clock definition and why do i need

    what is virtual clock in sta I knew this before but I am drawing a blank now.. so why not use a real clock to constraint the IO instead of using a virtual clock?
  3. S

    What language format is Credence Quartet using?

    Any one have any idea on what language format Credence Quartet uses and if it has the capability of dynamic inputs? So if I want to put in a lot number to identify some parts dynamically, can I do that?
  4. S

    Synopsys. 2007.03-SP*

    Yeah I think its rumor also. I checked with some other sources, no one has heard of it. Sorry if I alarmed anyone..
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    Synopsys. 2007.03-SP*

    No just hearing rumours, so trying to verify it. Just got off a meeting with Synopsys, they deny it.
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    What is clock uncertainity and why does it happen?

    clock tree jitter analysis Let me see if I remember this correctly. From a synthesis point of view, you apply clock uncertainity and clock skew the same way. But if you are trying to understand what they mean in a physical domain, clock uncertainity is some margin that you add to the clock...
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    Synopsys. 2007.03-SP*

    Guys any one have any experience with synopsys DC 2007.03-SP*? Any one have any experience in registers being optimized out when they are not suppose to be optimized out? I have been hearing about this through the garpe vine and was wondering about the validity of this statement. Thanks
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    Power disipation comparisson between WC and BC libraries

    Thanks for your comments guys. So from what I understand BestCase libraries should have more power consumption, which can be counter intutive if you go by name only. But if you go with the meaning, ie Best Case Libraries means faster chips, ie draws more power, it makse sense. This also...
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    Power disipation comparisson between WC and BC libraries

    Got a question. Would Power Dissipation numbers for a design with BC libraries be higher than WC libraries? I would tend to think yes., but I am not sure. Can some one please explain why? Thanks in advance
  10. S

    Difference betwen analyze -f verilog and read_verilog in DC

    read_verilog -netlist How are these two commands different? analyze -f verilog read_verilog
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    reading parameters for Elaborate command in Synopsys DC

    Hi Guys Can you give me the syntax to include it, I am not sure I understand. In a normal flow I would do something like this: elaborate top -param "abc=123, \ def=567, \ ghi=890" What would my syntax be if I had file called...
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    reading parameters for Elaborate command in Synopsys DC

    Does any one know how I can read in a file containg some parameter definitions for elaborating a design? I know I can do "elaboarate -param xxxx=abcd, ... " However how can I do this if the parameters xxxx=abcd are listed in a file?
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    How to change the font cases in TCL?

    Anyone know how I can chabge case in tclk? For example if I have "RITE" I wante "rite" for my script, how would I do it? Thanks
  14. S

    Help me understand the Bits through Queues paper

    Any one interested in discussing the paper "Bits through queues" by Anantharam Verdu? I need to understand this paper so that I can write something on it.
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    VERIFICATION METHODOLOGY

    I dont know much about queues. But there is a paper on "bits through queues." Its kind of a hard paper to understand, I am still working on understanding it for the past few months. Anyways, the paper talks about bits through queues and how you can have a capacity more than the channel...

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