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i think that these optimizations are from your design.you can check your netlist and check which port is tied high or low. then trace back to the rtl. you can find why the dc optimize the rtl.
when i synthesis the design, DC reports that there is a timing loop,
it was caused by the following code
assign mux_a = (en) ? b : mux_a;
This is the combination logic loop? Should I change my rtl code?
Re: DC - Identify scan pins
Hi wadaye,
Astro will reorder the scan chain and need the DC to generate a script which defines the scan chain in and out port .Do you know which command of the DFT compiler can do that?
Thank you!
hi all!
I am sure the sdf file has been annotated to post layout netlist!
but in wave trace,I can't see the delay. For example, the clock propagated throgh the clock tree.
thanks a lot!
thank you!
my simulation is reading the data from the cpu rom continously,4 times once.
the first three words is readed correctly,but the fourth word is wrong.
I think if there is timing violation,the former operations should be wrong either.
00000000 + -------+00000+ --------+
clk000...
hi all:
I have a problem!
when I simulate my netlist from Design Compile with NC verilog, it is ok!
but when I simulate my netlist dumped from Astro which just insert the clock buffer, I found the timing of the rom reading operation fail. and there is no timing information added in...
thanks!
But I read some sdc files, i find that the designer add the set_propagated_clock constraint for every clock. and there is no one in my sdc file. Is the file uncomplete? Will this item affect the clock tress synthesis!
sdc constraint file format
.tdf file is just for you to floorplan the pad positon.you should write it youself.
the file includes the position of the power pad!
hi all!
when i begin to load my sdc file which is the outputed file of Design Compiler,
what should I pay attention to ?esipically the clock signal.Should I change some setting ? Thank a lot!
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