the netlist difference between DC and CTS

[seu_noop]

hi all:
I have a problem!
when I simulate my netlist from Design Compile with NC verilog, it is ok!
but when I simulate my netlist dumped from Astro which just insert the clock buffer, I found the timing of the rom reading operation fail. and there is no timing information added in the simulation. we just verify the funcion of the netlist.
Does the clock buffer inserted affect the netlist?Can the netlist dumped from astro after cts operation without timing backannoted be simulated by NC verilog?
what happenned to the netlist when the clock tree synthesis done?
thanks a lot!

 

[lijian_18]

After CTS, main clock needs to travel through a lot of clock buffers to reach the register's clock. Though no timing information is included, simulator recognize this as several delta delays. How many levels of clock buffer will cause how many delta delays. So there'll be timing violation if different flops with different stages delta delay's clock.

 

[spauls]

Include SDF also , generated by PT , with actual wireload models,

 

[seu_noop]

thank you!
my simulation is reading the data from the cpu rom continously,4 times once.
the first three words is readed correctly,but the fourth word is wrong.
I think if there is timing violation,the former operations should be wrong either.

00000000 + -------+00000+ --------+
clk000 ___|000000|______|0000000|______

0ad0 ad1 ><00ad200>
data000000 ><00wrong >

the zero is just for printing and it is no meaning.
the data and address should come at the same time !but the data is later and wrong. it should be the data at address ad1 . but it is the data of another address and it is not the data at address ad2.
Does the buffer number of the ad clk and data cause this problem?

can some one give me the explaination of the event drive simulation or some suggestion?


thanks a lot!

 

[JesseKing]

you should simulate it with sdf.

check it again

best regards!