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Re: Hold and Setup
After you have completed post-route, you can do back-annotation.
This will put in the wire load delay etc and hence, you can check your setup/hold time.
Maybe you can try to change your code before the power compiler. i.e. you invert the clock before you pass the clock to the posedge clock_gating cell. This way, it will be negedge triggered.
Then, you add multiplexors so that during scan, you bypass the original clock and use your scan clock.
Just a thought:
Prehaps, u would need to use another faster clock to sample the data. implement an xor gate and count the number of "H" and "L". Then, based on the frequency of the sampling clock and the frequency of the two signals, you should be able to calculate the phrase difference.
Hi,
First of all, thank you very much for the reply.
So does that mean that the actual circuit that would be synthesized is actually multiplexer and gates?
i.e. for A <= A << 1, we expect a flip-flops when clocking is available. Now that the circuit is in parallel, does it means that it is a...
I think that the problem is with 2 parts. I will try to explain the first part.
The problem is that you are "confusing" the compiler when you lump lots of conditions in the process statement.
i.e. --> if clock'event and clock='1'and reset='0'then
I assume that you want a circuit with...
But, in this case, how does the circuit know when to shift the data?
for the case that a clock exist, data is shifted in every clock cycle.
But, for this case, since there is no clock, how to determine if the data have been shifted in and how to assert that the data shifted in is correct?
Re: verilog question
Typically, when you attempt detect 2 edges, the expected result is a flip-flop. With one signal to the clock and the other to the reset pin of the flip-flop. Thus, I think that if you want to detect 3 edges, it should be synthesizable under the condition that, you have a...
I have a question.
What is the circuit for shift register without clock?
Just an example, say I have a verilog code as follows:-
reg [15:0] A, B;
reg [15:0] C;
integer i;
always @(A or B) begin
for (i=0; i < 16; i = i + 1) begin
if (A>B) begin
A = A << 1...
Re: Pulse detection
I don't quite get what you mean. But, the inverted output, Q connected to the D-input -- This is a frequency divider. i.e. the clk frequency is divided by 2. Where is your pulse connected to?
Re: Pulse detection
You can use a D-FF. Just feed the pulse to be detected onto the CK signal and tie the D input to a fixed value (say "1").
This way, when there is a pulse, the D-FF will output a "1".
Note that I assume that you will have some reset circuitry to reset the DFF after...
It really depends on your circuit. I assume that you are talking about a flip-flop here.
For Synchronous reset:
Now, if you use synchronous reset, there is a setup time that is required to be satisfied before the circuit is reset. Typically, if reset and clk is on the same edge, the circuit...
veryfault
Thanks a lot.
But, I went into the directory, however, unfortunately, there is no pdf files there.
I saw lots of files with the extension .obk and one with .mtd
But, they don't open with acroread.
Could you upload the manual or give me a link to download it?
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