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Recent content by SergeyBondarev

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    SOPC builder- how to connect control signal for demux/mux

    SOPC builder demux/mux Hi, How is it possible in Altera SOPC builder to do demultiplexing/multiplexing tasks? Currently I'm developing video system and want to implement built-in algorithm like Median filter. I want to work the filter e.g. when SW[0] = 1 and disable it, when SW[0] = 0. I've...
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    zoomIn and zoomOut in laker using mouse wheel?

    Laker Zoom Hello! Anyone uses zoomIn and zoomOut in laker using mouse wheel? How can it be adjusted to use mouse wheel? Involving <Btn4Down> and <Btn5Down> to the file "leoDsgWnd.menu" gives no result. Thanks, Sergey
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    DE2 TV demonstration example

    Hello guys, I want to launch TV demonstration example for Altera DE2 board using PAL input signal. The example is built for NTSC input signal, and works fine. I looked into the datasheet of the TV decoder and corrected register initialization data in the verilog file "I2C_AV_Config.v" to...
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    How to find the metal thickness?

    In the PS (Process Specification) file for the technology
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    how to calculate the i/p and o/p resitance in spectre

    As usual, apply voltage or current source and take current or voltage. Then divide in calculator.
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    Skript for special calculator functions (ADE)

    Hello, Maybe someone knows where can I find the script for special calculator functions in ADE? For example I would like to know the skript for "bandwidth" function, in other words how it is implemented. Does it exist somewhere? Thank you for your reply Best regards
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    Virtuoso Layout and Labels

    Press Sheet->Edit size. Choose size of the frame(A, B...F). Date is in the right lower corner of the schematic. It is self-updated.
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    How to get the Ro of nmos in spectre or in Hspice

    Re: How to get the Ro of nmos in spectre sim Connect the voltage source Vds to the drain of the transistor and change it in DC or TRAN. Gate voltage is fixed. Calculate the current Ids through the voltage source. The output resistance will be equal to Vds/Ids.
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    Suggestions of PLL design books

    Re: PLL design Phase-Locked_Loops_Design__Simulation__And_Applications_5_Ed_Best_R_E__2003 search at ebookee.com
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    How to determine the Dumping factor in third order PLL?

    Re: Third order PLL Refer to "Phase-Locked Loops/Roland E. Best", Chapter 4: Higher Order Loops. The main problem - stability of the loop. You should choose the proper phase margin at the transit frequency ωT. The phase margin is correlated with damping factor in the second-order systems. What...
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    Channel Length for Analog Design

    The main problem if you will use the minimum dimensions of the transistors is the technology mismatch. For example, minimum length = 0.5 um. And you use two transistors in the current mirror. Let the maximum technology deviation be 0.1 um. So now one transistor has L = 0.4 um and the other has L...
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    Frequency range of the VCO

    Hello, Could you answer me, please, how to design the VCO for frequency synthesizer? The problem is that the frequency range must vary from 2 MHz to 64 MHz. I can obtain only from 10 to 50. My schematic is simple multivibrator. The voltage controls the gate of the lower Nch transistor, which...
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    How to measure the CMRR of an OPA on CADENCE tool?

    cmrr waveform See the book of Allen, Holberg "CMOS analog circuit design". There exist the measurement procedure of the OPA and the correspondent circuit for CMRR measurement. (page 430)

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