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Recent content by segabird

  1. S

    question about spectre PSS/Pnoise on Sampling & Hold Cir

    switched capacitor noise pss pnoise The following is the detail about previous question. My circuit is a quite typical folded cascode amplifier with pmos input. There are two AUX amplifiers working as gain booster on cascode NMOS and PMOS, respectively. There are several questions I want...
  2. S

    question about spectre PSS/Pnoise on Sampling & Hold Cir

    spectre pss pnoise I have run a PSS/Pnoise analysis for my sampling & hold circuit. The structure of circuit is switched capacitor, flip around with a gain-boosted amplifier. When printing noise summary, I found the top 8 noise contributers (they generated 70% of total noise) are not from...
  3. S

    question about spectre PSS/Pnoise on Sampling & Hold Cir

    I have run a PSS/Pnoise analysis for my sampling & hold circuit. The structure of circuit is switched capacitor, flip around with a gain-boosted amplifier. When printing noise summary, I found the top 8 noise contributers (they generated 70% of total noise) are not from main amplifier, but...
  4. S

    The Best University for analog IC design in Europe?

    Are you the author of the paper "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC"?
  5. S

    Guess what this circuit is for !!! :)

    Can you give me some points for downloading data? Achieving points via answering question is so slow,haha. Just a joke,hoho
  6. S

    Analog IC Interview Questions

    what are the problems??
  7. S

    question about small signal figure

    In the figure 3.28 of razavi's book, why the ro of M1 is absent ? (The figure is small signal figure of soure follower and the M1 is the input NMOS.)
  8. S

    Which architecture suit for 60MSPS 6bit ADC?

    Is the function of folding circuit in folding adc the same as the subdac circuit in the pipeline ad?
  9. S

    How to get 12-bit SAR ADC without self-calibration using CMOS process?

    Re: 12-bit SAR ADC The product ID is AD7450.
  10. S

    Open Loop and Closed Loop

    This is correct. But the 3db BW is different between open loop system and closed-loop system.
  11. S

    multi-channel ADC design architecture

    According to your spec 200Mhz 8~9bit, I think fold or pipeline are the choise and the others are not suitable.
  12. S

    How to get 12-bit SAR ADC without self-calibration using CMOS process?

    12-bit SAR ADC There is product in Analog Device which is 12bit SAR ADC without selfcalibration. I am sure that.
  13. S

    Open Loop and Closed Loop

    This confused me and which is not correct in the current feedback system? My opinion is that the 3db bandwidth of close loop system is BW/As.(Bw is the unit gain bandwidth of open loop system and As is the Gain of close loop system)
  14. S

    Where to get QPSK Modulator with I/O = 1Mbps/100Mhz RF?

    Re: Question about buffer 3x, Can you give some opinion about the order about the bandwidth in this case.
  15. S

    Where to get QPSK Modulator with I/O = 1Mbps/100Mhz RF?

    Re: Question about buffer thank u for your help. we can use clear supply for simulation so the noise in the supply will not be calculated. but i want to know which order of the bandwidth is needed in the case. In the application this buffer must drive out a big capacitance so i want to design...
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