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Recent content by seemagoyal44

  1. S

    What are the differences between PLL and DLL in advanced FPGA architecture?

    what are the differnce between PLL and DLL in Advancded FPGA architecture
  2. S

    What are the timing parameters related to PLD?

    what are timing parameters -clock to output delay and system clock to system clock delay related to PLD
  3. S

    which ie better nand or nor latch?why

    i wann to know which latch is better nand or nor latch?and why
  4. S

    Help me write a test bench for full adder and 4:1 mux?

    can anyone help me out for writing test bench for full adder and 4:1 mux
  5. S

    How to design ( a.(b+c))' using CMOS?

    can anybody tell how to design ( a.(b+c))' using cmos
  6. S

    How to design a+(b+c)'+c using CMOS?

    can anybody tell how to design a+(b+c)'+c using cmos ....2nd term b+c)' is nor gate but how to add a+c with nor that i don`t understand
  7. S

    Help me design an alu that performs logical and logical xor

    design a alu that perform ...logical and..logical or..logical xor..logical x nor and complement functions
  8. S

    Need VHDL code for building a 16bit counter with synchronous load

    \i wann a vhdl code for... build a 16 bit counter with synchronus load and asynchronus reset . the outputs are three states outputs ,controlled by two seperate signals-one for the lower 8 bits and one for the upper 8 bits . inputs: clk,reset,load,data {15:0],upper_en,lower_en output:count[15:0]
  9. S

    How to design 4 bit counter using hald adder circuit ?

    design 4 bit counter using hald adder circuit
  10. S

    vhdl code--parity inserter

    write a vhdl code for 4 bit parirty inserter circuit that takes 4 bit data,calculates even parity and insert parity bit at output line
  11. S

    Help me design a delta cycle for these outputs

    write delta cycle for each output of following code;;;; architecture delta_bev of delta is begin z<=not y; y<=w or x; x<=u or v; w<=u and v; v<=c or d; u<=a and b; end delta
  12. S

    Looking for a phase shifter device (by 90 degree)

    i want a circuit or a device that shift the signal by 90 degree.
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    Help me design a State machine for Traffic Control at a Four point Junction.

    state machine i don`t have this book...can anyone help out... Design a State machine for Traffic Control at a Four point Junction. ..there are no further specifications for this question[/code] Added after 1 hours 2 minutes: i wann the complete answer for this question
  14. S

    Help me do two FSM design tasks

    Re: FSM questions i wann this answer using fsm.can u help out in detail
  15. S

    Help me do two FSM design tasks

    1.Design FSM that accepts all strings over 0 and 1 such that last bit have at least two 1's .Not to use more than 4 states. 2.design fsm that does 2/3 of input fruency .if input is 100 mhz and o/p should be 66mhz.
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