seemagoyal44
Member level 1
\i wann a vhdl code for...
build a 16 bit counter with synchronus load and asynchronus reset . the outputs are three states outputs ,controlled by two seperate signals-one for the lower 8 bits and one for the upper 8 bits .
inputs: clk,reset,load,data {15:0],upper_en,lower_en
output:count[15:0]
build a 16 bit counter with synchronus load and asynchronus reset . the outputs are three states outputs ,controlled by two seperate signals-one for the lower 8 bits and one for the upper 8 bits .
inputs: clk,reset,load,data {15:0],upper_en,lower_en
output:count[15:0]