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Recent content by se7ensong

  1. S

    simulator options for low power

    Hi, I don't know the answer, but backward integration is always stable. I know some forward integration algorithms will causing non-convergence problem. But I don't know why it is particular important in low power range ... Could you please help me?
  2. S

    what is an 'rc technology file' in PDK??

    If you need build accurate inductors, I suggest you do ADS or momentum. I know some PDKs do inductance extraction, but the kit designer told me it's not that accurate.
  3. S

    create .SCS file to cadence design

    Please be clearer. I am not sure what do you want to do. If you want to create your own OTA based on your design, just draw the schematic.
  4. S

    what is an 'rc technology file' in PDK??

    I have seen your other thread of PEX extraction. Yes, inductance extraction depends on the models provided by your foundry. I believe you need to contact TSMC for more info.
  5. S

    Layout of capacitors

    Yes, then my reply shows the way to go. Another way is to use skill script to draw and connect the whole array. You can do it fast if you are familiar with it. Otherwise, just use the method I mentioned for a simple array.
  6. S

    Offset voltage measurement

    Starts from the definition: "The input offset voltage (V_{os}) is a parameter defining the differential DC voltage required between the inputs of an amplifier, especially an operational amplifier (op-amp), to make the output zero (for voltage amplifiers, 0 volts with respect to ground or between...
  7. S

    Layout of capacitors

    What do you mean by "using arrays"? Do you mean drawing a cap array? In cadence layout, you can draw one unit cap first then select and copy them. Then before you paste them, press F3 and you will get a window where you can change the number of rows and columns that you want to paste.
  8. S

    Virtuoso Schematic XL-Matched Length Constraint

    Sorry I don't have an answer, but want to share my experience. Matched Length Constraint is the correct one to use, but would be hard to met the requirement. In Cadence, you can see the length of each segment of the connection, but not all of them. So matching them by hand requires a lot of...
  9. S

    I have this error on cadence , any help ?

    Check "vpulse" in the analogLib. Just put the pulse period longer than your simulation time.
  10. S

    switch operation in cadence analog lib.

    It is a switch not a clock source. You should use vpulse in the analog Lib.
  11. S

    Body bias related question

    I agree with Dominik, you have to first check which technology you are using. But it shouldn't be a problem as most process now use p-sub so PMOS is definitely in it's own n-well. Therefore, your input PMOS pair should be fine, but at a cost of larger area (you cannot share n-well with other...
  12. S

    How to drive a series LC resonance circuit?

    Thank you so much guys for the suggestions. I am really considering to use a bipolar RF transistor to provide the current. biff44, thank you so much for the comment on the measurement. I will pay attention to this problem next time. This size of the coil (build on a PCB) is indeed very small...
  13. S

    How to drive a series LC resonance circuit?

    Thank you so much. That's a lot information. I will read them first.
  14. S

    How to drive a series LC resonance circuit?

    Dear goldsmith, Thank you so much for your reply. I understand the matching is very important when connecting to an antenna. But since I am connecting to a serial LC circuit, I am not sure how to do the matching now as when in resonance, what left is only the resistance of the inductor which is...
  15. S

    How to drive a series LC resonance circuit?

    Hello there, I am designing an near field inductive link at 900 MHz. For some reason, I need to 1W at transmitting coil which is a serier LC circuit. I am trying to drive it with a 900MHz 30dBm Power Amplifier. My question is, do I need to match the impedances of the PA and the LC in...

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