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hi,
I used the circuit as shown in the attached file. It is a frequency comparator based on a PFD. The problem is I need to write the reference source of this circuit for a study. If you know any paper contains the circuit please tell me the title.
Thanks.
hi,
I usually use Virtuoso LE and Virtuoso XL. Now we do not have VXL license but have Virtuoso LE Turbo.
What is the difference between VLE Turbo and VLE? are there some features of VXL (like connection mapping) in VLE Turbo?
Re: about mfg grid
you can check the minimum grid from CIW windows:
Tools --> Technology File Manager ... --> Check.
If your set-up grid smaller than that, your layout will not pass DRC (if the Switch for grid is enabled)
hi all,
I just installed a PDK. When I generated the layout, I only got blank box without being able to see the layer. If I prese Ctrl-F, "pcellEvalFailed" label are shown.
I found that one of the problem source is that the correspondent layout.cdb points to wrong directory; the warning when I...
Re: calibre LVS errors
hi i found the solution for this problem.
the case is that the netlist extracted from the schematic needs further process.
to do this, after you open and set up the calibre lvs,
on the menu bar, select: Setup->Preferences->Triggers
on the first box paste a link some thing...
Hi, I have the following case which needs a method to compare netlist or circuit behavior in cadence environtment.
My case can be illustrated like this:
I have, says, a digital circuit whose name is A and its function is:
A= B.C.(D+E) + E.(D+E)
Since there is redundancy on the term "D+E" and...
hi,
i run nanosim for transient simulation. whenever i set time simulation more than 100us, the results beyond 100us are strange. i thought first it was a problem on my circuit but, it consistently shows this strange results. is there any of you who experience the same problems?
The circuits...
nanosim works with hspice/ spice netlist files, right?
1) if you have the layout and the schematic as well as the RCX/ PEX extractor like assura and calibre, then the work will be very simple; you just extract your layout, and then by using config for hspiceD you can set up a post simulation...
Re: "GROUND && ! POWER": no POWER nets pre
maybe you have to change the layer for the pin name (that text you can read). for some PDK it has to be "drawing", but can be "pin" or "label" for the other.
Re: spectre vs config
i think if you want to run a post sim using ADE, using config is more flexible to change from one view (says schematic) to another view (some thing like av_extracted).
if you want to use netlist i think it is better change it into a model (using .include, without deleting...
hi,
I actually still cannot solve too, but now i can run a netlist generated using calibre PEX by someone else. it has to be set up as a model. a guideline has been posted here...
thanks for all reply, I found the source of the problem.
prior to running Calibre, I have to setup first the map file and the include file
Calibre -> Setup -> Layout Export: Fill in "Layer Map File" with right file name and location
and
Calibre -> Setup -> Netlist Export: Fill in "Include File"...
many thanks for the reply, I found out the source of the problem. It says:
"Rule File Pathname: .../_cmrf8sf.drc.cal_
((20*M3) + (Pfet S/D not over T3)) / (NW union PI) ratio >= 0.20"
This means that the area of M3 connected to NW is too small (still less than 0.20).
Since NW is usually...
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