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I'm doing the layout for my RFIC. Since the IC doesn't have ground plane, it is difficult to get a good ground. I saw lots of people used bypass capacitor, but I'm confused about where they put the other terminal of capacitor in the layout. For example, the cascode gate need a bypass capacitor...
sorry for the confusion, I mean the amplifier's input bias voltage. I build a fully differential amplifier with around 100dB open loop gain, when I connect the output to input, the output stage voltage affect the input bias voltage and the amplifier is not working anymore.
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The fully...
I'm building a low pass filter with fully differential amplifier. For the fully differential amplifier, how could I prevent the input dc bias affect by the feedback loop? Should I add a dc decouple capacitor? Is there any method I don't have to add a dc decouple cap?
Thanks
Hi everyone.
I'm learning RFIC design now. I have a LNA works at 35GHz with SiGe. I designed a LNA that using common emitter with cascode method. In schematic simulation, the LNA is stable. However, the RLC extracted results shows the circuit is unstable.
I think one of the reason is that the...
Thank you for your reply. What I don't understand is unconditional stable means the amplifier will be stable at any load condition. why I cascade another amplifier, which input impedance is R+jX, could cause unstable condition?
I'm trying to cascade 2 LNA together to achieve higher gain. Both LNA are unconditional stable (kf>1 and b1f>0), but when I cascade them together, they are unstable （kf<1）. Does it mean the cascade of 2 unconditional stable LNA is not 100% unconditional stable?
My input voltage is pretty small, so 30dB will not distort the signal. My first design was close loop, but the bandwidth is not enough because of the feedback and phase margin. I thought the open loop don't need to consider about the phase margin, which could lead me have more bandwidth. Do I...
Hi,
I'm designing a fully differential amplifier. My block include a amplifier 30dB gain open loop and a common mode feedback circuit with 20dB gain.
when the input have dc offset (0.1V), it saturate the output, so one output port of differential amplifier's voltage reach VDD, which is turned...
Hi Bigboss
How should I match cg output? I simulated the S22 on smith chart and it is almost pure imaginary part. I tried to add some L or C to match to 50ohm and it is not work.
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My frequency is 40GHz. I want to cascade 2 cs with cascode lna to reach the gain of requirement.
I want to design a four stages lna. It use a common source w/ inductive deg as input and cascode a common gate as second stage, and then use another cs w/ind deg as third stage and cascode a cg again. my question is do i need to make each stage match? like first stage's output impedance match...
Hi all,
I want to bias my transistor by using an large inductor. At the same time, I want to shunt a capacitor at power supply. How should I choose the value of inductor and capacitor, at the mean time I can filter the noise?
I'm also confused about the noise. Is the noise come from power...
Hi all,
I just updated the version of my ADS. To design a LNA, I made PAD layout for my amplifier because the ADS lib doesn't have the package layout for the amplifier.
I use component -> edit component artwork to import the layout to the amplifier, but I can't change the component layout type...
I'm trying to simulate the IP3 with matlab. I find if I use 2 CW tones as Jammer, the iIM3=3*Pji-2*iIP3. However, when I replaced the CW tone with bandlimited Gaussain noise, which means the Jammer has the bandwidth like 1MHz. The IM3 reuslt that I simulated had higher power than the formula...
Hi guys,
I am trying to simulate the 3rd intercept point with matlab. First, I generated 2 CW tones and it gave me the correct power of IM3. Then I generated a random noise signal and pass it through a bandpass filter, which gave me 2 tones with 1MHz bandwidth for each tone. The simulation...
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