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as title, i want to generate a saif file using verilog rtl simulation.
but when i run the command, the terminal shows the error message as belows:
$set_toggle_region(test.dut1);
|
ncelab: *E,NOTSYT (./rtlsim.pat, 127|21): Unrecongnied system task or function (did not...
Thank you for ur suggestion.
there is one thing make me confuse. that is first time i verify the rtl vs netlist. the netlist is produced by compile option in synthesis tool, the formal is ok. But when i take the netlist file that is produced by compile_ultra option in sythesis to do formality...
hi guys:
i perform the verification for rtl vs. netlist.
i encounter a problem in the match stage of formality.
there are some of unmatched points in the reference object, but these unmatched points do not appear in the implementation object.
the type of unmatched points is DFF.
pls tell me...
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