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Recent content by sazjad

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    Noise Margin Analysis for Dynamic Logic circuits

    Hi, I am trying do the noise margin analysis of a dynamic CMOS logic circuit (Domino) which is run by a clock signal. Now, what should be the procedure to do that? I am trying to follow something similar to standard method of measuring noise margin for an inverter using VTC curve. Thank you...
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    Need the code for testbench componets for AMBA APB written in systemverilog

    Hello ALL I am trying to develop the testbench for AMBA APB in Systemverilog Can anybody help me with that? Thanks Sazzad
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    Need some help to get a solution for SoC Encounter 9.1

    Hi all..... I am now learning the Place and Route using SoC Encounter version 9.1. But the document given with this version is compatible with the earlier version (Version 8.1). So, some of new tool functions are not described properly in this document. E.g. in the document there is an...
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    how interconnect length depends on fanout

    Re: auto wire load Can anyone send me ( or give link) some files of Design Compiler User Guide for doing Synthesis and STA. I have the tool , but i don't have the tutorial/documents. Specially i want something good to learn synthesis scripting and how to write SDC file and all those things...
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    clock tree synthesis versus logic synthesis

    Dear eda_wiz I found your answer interesting! Can you give me some clear idea about heavy load(capacitance) on clock net?? I mean how clock net gives rise to heavy load !!!! Thanks in advance sazzad
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    Techniques for reducing insertion delay

    Hi all... Regarding one of replies:- Dear rkadarla, i found your answer interesting !! Can u please give me a clear and detailed idea about what u really meant by cutting long nets and add buffers? Actually i want to know is there any relationship between cutting long nets and adding buffer...
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    [SOLVED] Need Some files to Practice place & route in SoC Encounter version 8.1

    Hi lohi21, Thanks for your comment. yes u r right, that's why i am searching for a complete package from a single source. By the way, the link u have given is very useful. Thanks for that :) ---------- Post added at 22:55 ---------- Previous post was at 22:51 ---------- Hi rca, Thanks...
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    [SOLVED] Need Some files to Practice place & route in SoC Encounter version 8.1

    Thanks kumar_eee for your message. I found this DTMF folder. But still i have a problem !!! To work with these files in DTMF folder i need to download the Artisan 180nm library from Cadence Learning Management System websites which is actually free. But somehow i could not get into that site...
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    Need Some files to Practice place & route in SoC Encounter v 8.1

    Hi..... I am now learning place & route in SoC Encounter version 8.1. As far as i know to run/practice i should have 1.a verilog netlist(*.v) 2.a technology file (*.lib) 3.a LEF file for the library(*.lef) and 4.a script file(*.conf). But except verilog netlist i don't have any of the above...
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    [SOLVED] Need Some files to Practice place & route in SoC Encounter version 8.1

    i see.... that's a problem !!!! right now i don't have any access to such data !!! :(
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    [SOLVED] Need Some files to Practice place & route in SoC Encounter version 8.1

    Hi.. ya , but still i am wondering if i could find something that is using at any school or training institute for training purpose. Actually without these files i can't practice well !!
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    [SOLVED] Need Some files to Practice place & route in SoC Encounter version 8.1

    Hi..... I am now learning place & route in SoC Encounter version 8.1. As far as i know to run/practice i should have 1.a verilog netlist(*.v) 2.a technology file (*.lib) 3.a LEF file for the library(*.lef) and 4.a script file(*.conf). But except verilog netlist i don't have any of the above...
  13. IMG 3962

    IMG 3962

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    • Album: My photo
  14. My photo

    My photo

    • sazjad
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