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Recent content by Sathishkrishna10

  1. S

    How Jumper insertion reduce Antenna Effect ??

    during metallization wires will be left floating, so that it will be act as temporary capacitor and collects charges. while using jumper every metal in same connection left floating during each metal etching process and collects charges. the wires left floating until all metal layers are etched...
  2. S

    How addition of dummy transistors reduce Antenna Effect ?

    why we go for "Transistor as diode" while we have actual diode. ????
  3. S

    How Jumper insertion reduce Antenna Effect ??

    Hi Erikl. if both are same, why we go for second one (jumper insertion) ??? how it works during ion imp/etch ??
  4. S

    How Jumper insertion reduce Antenna Effect ??

    Hi.. How the splitting of wires reduces Antenna Effect. I referred no. of docs. still i have more doubts in it. Am so confused with it. 1. In case of single long wire(M1) to gate, Assume the charge accumulated in M1 is 3x 2. In case of splitting the wire to 3 parts(M1-M2-M1)...
  5. S

    How addition of dummy transistors reduce Antenna Effect ?

    thank you Yadavvlsi. i read that if we use dummy transistors to reduce Antenna Effect, "Reverse Antenna Effect" will occur. What is Reverse Antenna Effect ?? How its differ from Antenna Effect ???
  6. S

    How addition of dummy transistors reduce Antenna Effect ?

    Hi.. How the addition of dummy transistors reduce Antenna Effect ?? can anyone elaborate this ??
  7. S

    problem with global connection UMC40nm

    Hi, In my block am using std cell which has global connections vdd!,gnd! & i must connect it with vdd & gnd respectively in top level. In layout i did it by connecting with metal. To connect in schematic i used "cds_thru" but still its getting error while running LVS (vdd,gnd shorts with...
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    [SOLVED] Synopsys LVS Error: What does this error mean?

    Hi Kriz, I couldn't get your attachment. . can you attach it properly again ??? or else can you type wats the error message that you are getting ?
  9. S

    Dummy poly consideration

    Hi. Until which technology node we can use dummy poly & why ? in TSMC above 60nm dummy poly getting off automatically. what is the reason for that ?? thanks in advance.

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