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Recent content by sathishkas

  1. S

    What is non-intrusive way of testing & intrusive way of testing in DFT?

    Hi, There are two types of testing in DFT. 1) non-intrusive way of testing and other is 2)intrusive way of testing the system. Can anyone explain what is the meaning of those testing in DFT? Thanks in advance.
  2. S

    Can people provide information on what is meant by Compression efficiency in DFT?

    Hi, Can people provide information on what is meant by Compression efficiency in DFT? What is ideally a good compression efficiency and its impact? How to achieve a good compression efficiency and what factors govern it? Please consider all kinds of compression architectures when you...
  3. S

    Why do we use negedge of flop to get a TDO value in BSCAN?

    Hi, 1) For the first question, you said that to avoid a Hold violation we are taking the output value at negedge. Basically, these BSCAN registers form a shift register to get a TDO value & moreover, we are using only one clock called TCk then, where will we get a hold violation? Please...
  4. S

    Why do we use negedge of flop to get a TDO value in BSCAN?

    Hi, 1) Could you please explain the reason why are we using negedge of flop to get a TDO value in the Boundary scan operation ? Why don't we get a value at posedge of clock? 2) Why Bypass Register is a 1-bit register? Without bypass register, why cant we bypass the operation? Thanks...
  5. S

    VHDL Simulation warning / Error

    Thanks for your reply. Now it's working fine. But When I simulate it, all my inputs/outputs are getting a value of 'U' (Undefined Value) moreover, I am not getting any waveform. Could you please tell me what are the things I should do to get the correct value while doing the simulation...
  6. S

    VHDL Simulation warning / Error

    Hi, I have written a simple D Flip-flop code and a corresponding test bench in VHDL code. While I compiled I didnt get any warnings/errors. But when I was running VHDL Simulation with NC-Sim I encountered the following error. I need to dump out the waveform and check the output. Should I...
  7. S

    What is the difference between Combinational ATPG & Sequential ATPG?

    Hi, Can anyone please tell the difference b/w Combinational & Sequential ATPG and at what stages it will be used ? For generating patterns for static & dynamic faults which one of these alg's are used? Thanks, Sathish
  8. S

    what's the differences between Latch and Flip-flop?

    Hi, Thanks for your reply. I have seen in some block diagram of latch which has only Enable signal. Moreover, I have seen video of Digital Electronics which was taken by IIT-Karagpur Professor even she told that latch does not need clock. I am totally getting confused with clock and enable...
  9. S

    what's the differences between Latch and Flip-flop?

    Hi, Can anyone please tell me whether Clock is needed for Latch? Some material they are telling that Clock is needed for latch & some other material they are telling that Clock is not needed only Enable will be used in Latch. Latch needs Clock or Enable? Please clarify my doubt. Thanks
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