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As you increase the capacitor value, the amplitude peak increases (for the same tail current). This could push the cross coupled transistor in to triode. In fact if the rds of these transistors reduce below certain value that reduces the effective Q of the tank(before they get in to triode), you...
On the choice of R-C vs C-R
1. If the R is implemented with MOS, then it has to R-C (fig(d)) as you can bias the transistor correctly and have fixed-R over output swing
2. In most cases the dominant pole is at the first stage output, so I would prefer to keep the capacitor end that displays the...
The capacitor helps reduce phase noise by providing class-C operation to your VCO.
In class-B, each section conducts current for half the time (180deg) whereas in class-C, the conduction angle is much less (say 100deg). In class-C current consumption of your VCO would rise greatly around the...
ac simulation would not work here as it operates around a bias point. Do transient analysis across frequencies. Or do you have this problem in transient analysis?
In that sense a^(-st) could be called as an eigen function and it could be written as e^(-st*ln(a)) so it only amounts to a little change of scale. Do you have any particular reasons to do this
The amplitude can be predicted and according to Vittoz,
where IB0 is the 0th order modified Bessel function, Ut is the thermal voltage, K is the factor by which the dVGS transistor is stronger than the amplifying transistor. V is the amplitude of oscillation and I is the settled bias current.
The change in the fundamental frequency may be too small to be observable, but the resulting phase noise would be. Note that the open loop circuit the phase noise would be higher in addition to the swing being dependent on supply, load and temperature resulting in greater phase noise during use...
Due to the non-linearity of the active device characteristic, harmonics of the fundamental are created which are fed back and gets mixed to create IMP that introduce phase distortion at the oscillation frequency (say 2*wo-wo=wo falls at the original fundamental at altered phase) that results in...
Do a pxf analysis and plot the outputs from the control voltage source (Signal) and the power supply (Noise). Look for the "-1" ref sideband to observe the frequencies that matter. Note their relative levels and model it as noise at the input of the VCO (or at the output) in the phase domain LTI...
This is not unexpected isnt it. You reduce the capacitance to increase the frequency keeping inductor and tail current constant, you should see increase in voltage swings. In most cases the amplitude variation of VCO output over frequency is not a problem. Do you really have a problem with the...
Unity gain configuration allows for large input step (max).
Slew limited part ends when the feedback takes control of the loop, so it is easy to see that the unity gain configuration would exhibit the same slew rate over a larger time/voltage that makes it easier to demonstrate and measure.
The...
As long as the loop does not lose lock during the step, linear assumption would hold quite well. The response shows no sign of losing lock., only overshoot, but I guess it could be designed for better stability
Not necessarily. Even for the basic amplifiers it would not hold in one direction.
ICMR for a complete amplifier would be limited both by input as well as output stages. If you see some sources pointing otherwise, please share.
120dB of dc gain for LDO!!. Just drop the gain to 60dB and you will have a very good design.
Not much could be told from the frequency plot. Would be good to look at the schematic.
6dB variation in gain with Common mode is expected naturally in R2R ip stages. If you want to make the gm constant with CM you have ways to do it, but first convince yourself that you cant do without it as it is going to cost you on other specs and effort.
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