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Recent content by saran826

  1. S

    What if power is connected to gate?

    Why we are not connectng VDD directly to a gate of a MOS?Usually through a tie high or tie low cell only we will connect. Why its flagging as ERC error?
  2. S

    will get antena effect in poly

    If I used poly for interconnecting 2 gates of long distance will i get antenna effect?please explain the answer in detail. Thanks in advance
  3. S

    What are the layout methods to make source to drain capacitance zero?

    What are the layout methods to make source to drain capacitance zero?
  4. S

    What things we need to take care a lenghty routing let's say 5000um

    Hi what things we need to take care of a lengthy routing of 5000um? what if its a voltage signal? what if its a current path? Please explain in detail what things we need to take care in these 2 cases?
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