Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by sarah

  1. S

    Verilog coding for ASIC vs FPGA

    Hi, Have this question, is verilog coding targetted to ASIC is the same if we want to target it to FPGA? tq in advance.
  2. S

    Modelsim gives an unexpected simulating result,why?

    Hi skycanny, echo47 is using conditional expression to get data_out output signal. You can use if else condition and get the same result. module counter (clk, clr, dir, ce, data_out); input clk, clr, dir, ce; output [3:0] data_out; reg [3:0] data_out; integer direction; always @ (posedge...
  3. S

    VHDL translation to Verilog Problem

    Could you provide the full code.... I couldn't get the whole picture unless you do. Thanks.
  4. S

    Does anyone has the RTL code of ARM AHB-to-APB bridge?

    amba apb protocol rtl Hi blueagate, I used to develop the bridge for the AMBA bus configuration, before end up using the AMBA IP from Synopsys. Whizkid is right, do read the AMBA 2.0 spec and put the emphasis on the bridge as well as the AHB and the APB protocol. Try grasp the basic idea of...
See more

Part and Inventory Search

Back
Top