VHDL translation to Verilog Problem

[angjohn]

i am having problem with translating from vhdl to verilog:

the VHDl code looks like this:
type states is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19);

what is the proper way to translate the above statement into verilog, can it be done by following statement:

parameter[4:0] S0 = 0;
parameter[4:0] S1 = 1;
parameter[4:0] S2 = 2;
parameter[4:0] S3 = 3;
parameter[4:0] S4 = 4;
parameter[4:0] S5 = 5;
parameter[4:0] S6 = 6;
parameter[4:0] S7 = 7;
parameter[4:0] S8 = 8;
parameter[4:0] S9 = 9;
parameter[4:0] S10 = 10;
parameter[4:0] S11 = 11;
parameter[4:0] S12 = 12;
parameter[4:0] S13 = 13;
parameter[4:0] S14 = 14;
parameter[4:0] S15 = 15;
parameter[4:0] S16 = 16;
parameter[4:0] S17 = 17;
parameter[4:0] S18 = 18;
parameter[4:0] S19 = 19;


the above translation is what i get from XHDL tranlator, from my point of view i think that is wrong. so, can anyone give me some guidance or advice to solve the above problem! thank you.

 

[sarah]

Could you provide the full code.... I couldn't get the whole picture unless you do.
Thanks.

 

[khorram]

Why do you think it is not correct? It is correct conceptually that assigns values 0 til 19 to S0 til S19. If you select another encoding style (onehot, twohot, ...), it will change. Maybe you expect to see the following result:
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9, S10 = 10, S11 = 11, S12 = 12, S13 = 13, S14 = 14, S15 = 15, S16 = 16, S17 = 17, S18 = 18, S19 = 19;

Regards,
KH

 

[jimjim2k]

i am having problem with translating from vhdl to verilog:

the VHDl code looks like this:
type states is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19);

what is the proper way to translate the above statement into verilog, can it be done by following statement:

parameter[4:0] S0 = 0;
parameter[4:0] S1 = 1;
parameter[4:0] S2 = 2;
parameter[4:0] S3 = 3;
parameter[4:0] S4 = 4;
parameter[4:0] S5 = 5;
parameter[4:0] S6 = 6;
parameter[4:0] S7 = 7;
parameter[4:0] S8 = 8;
parameter[4:0] S9 = 9;
parameter[4:0] S10 = 10;
parameter[4:0] S11 = 11;
parameter[4:0] S12 = 12;
parameter[4:0] S13 = 13;
parameter[4:0] S14 = 14;
parameter[4:0] S15 = 15;
parameter[4:0] S16 = 16;
parameter[4:0] S17 = 17;
parameter[4:0] S18 = 18;
parameter[4:0] S19 = 19;


the above translation is what i get from XHDL tranlator, from my point of view i think that is wrong. so, can anyone give me some guidance or advice to solve the above problem! thank you.

Hi

I Have used it in FSMs.

tnx

 

[angjohn]

thanks for the reply but i have found the problem already!! thanks!

 

[angjohn]

i now have a problem with how to write the code in verilog for LPM_RAM_DQ ram which is inside the maxplusII. can anyone tell me how to write that code or provide me the source code to implement LPM_RAM_DQ in verilog. Please. thanks!!!!

 

[nj_jack]

I think vhdl is very good, why not use it?

 

[vibhute_r_p]

Why done you use readymade VHDL to verilog convertors?