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Recent content by samuel

  1. S

    two questions as outswing and load capacitor!

    hello, erilk (1) when any transitor falling out of saturation, charge transfer is affected as the circuit above? That is to say, this circuit minimum outswing is about 2V, not about 1.6V? In fact, this circuit minimum outswing is about 1.6V. (2) how to calculate the circuit load...
  2. S

    two questions as outswing and load capacitor!

    (1) what is the operational amplifer outswing as showing? the nonliear show what? (2) the load capacitor of this circuit? how to design this amplier SlewRate?
  3. S

    0.35um 3.3V NMOS transistor with gate applied to 5.0V, it is ok?

    thanks, kemiyun in this case, first i want a larger moscap in my 5V circuit, so i want replace the thick NMOS(5.0V)capacitor with thin NMOS(3.3V)capacitor; second , i find the Vbd(breakdown voltage) is 6.5V, so i think that. third, in my application , nmoscap...
  4. S

    0.35um 3.3V NMOS transistor with gate applied to 5.0V, it is ok?

    hello ,everyone Now ,I want a moscap with inversion mode. can i apply 5V to 0.35um_3.3V_NMOS gate? if not, why?
  5. S

    synopsys installer error,why?

    install_bin/Linux/bin/wish: line 1: ./wish8.4: No such file or directory
  6. S

    how to simulate the noise of this circuit as attached picture

    switch noise: all switch noise and photodiode noise.
  7. S

    how to simulate the noise of this circuit as attached picture

    how to simulate the noise of this circuit as attached picture
  8. S

    why pip capacitor can not be extracted from layout?

    why pip capacitor can not be extracted from layout with calibre? lvs report appears: pip capacitor can not be extracted!
  9. S

    the influence of temperature on ESD circuit?

    hello everyone, I had designed a chip. in the normal temperature, the test of the chips are ok; but after higher temperature(125 ℃) and low temperature(-55 ℃) tests , a problem happens to some of twenty chips , that is, the current of the wrong chips become larger. I had check the wrong chips...
  10. S

    I am designing a bandgap with ppm<10 and vref=2.5

    palmeiras hi, palmeiras in the course of designing the bandgap chip, I had simulated that from -40 to 80in dc scan means, the simulated results shows ok. thanks anyway. palmeiras
  11. S

    I am designing a bandgap with ppm<10 and vref=2.5

    Hi,palmeiras the designed chip had been tapeout, the above results are not simulation data but test data。 the architecture of bandgap is Banba。 I feel that the variations are obvious in lower temperature , why? I remember I have simulated that from -40 to 80, it is ok.
  12. S

    I am designing a bandgap with ppm<10 and vref=2.5

    my test results as follows, -40 (degree) 2.848(V) -30 2.68 -20 2.531 -10 2.38 0 2.28 10 2.223 20 2.213 30 2.203 40 2.199 50...

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