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Recent content by sally wang

  1. S

    Can I use VHDL Test Bench for Verilog in Xilinx ISE 8.2i software?

    Hi, can Verilog & VHDL use the same test-bench? I mean, can I use VHDL Test Bench for Verilog in Xilinx ISE 8.2i software?
  2. S

    When to us assign and always in Verilog HDL?

    ques on Verilog HDL in Verilog HDL, when should I use 'assign', and when use 'always'? Anyone understands this area can help me modify this Verilog code? module led1(CLK,SMP,OVR,UPL,TRG); input CLK; output SMP,OVR,UPL,TRG; always @ (CLK) SMP <= 1'b0; OVR <= 1'b0...
  3. S

    what "16'h0" means in Verilog HDL?

    Anyone knows what "16'h0" means in Verilog HDL? Thanks
  4. S

    How to modify this VHDL code?

    thanks for your help!
  5. S

    How to modify this VHDL code?

    Hi, I'm now trying to write a VHDL code for LED controll system. But why there is always an error says: 'Object O6 of mode OUT can not be read'. How to modify that? entity led1 is Port ( IO_L1P_D31_LC_1 : in STD_LOGIC; IO_L1P_D30_LC_1 : in STD_LOGIC; O6,O4 : out...
  6. S

    Control LEDs ON/OFF using VHDL

    Hi, I'm trying to develop a VHDL code for LEDs control. Is there anyone can help me? Here are some relative attachment. STB - Standby PWR - Power On TRG - Trigger UPL - Upload OVR - Over Range SMP - Sample CLK - Clock Active IDL - FPGA RDY/IDLE
  7. S

    question of testbench

    I've already figured out the problem. It's bcoz I selected the vhdl file but not the test-bench file to generate behavioral model, so that it's undefined. Thank you for your concern!
  8. S

    question of testbench

    when write a testbench of VHDL, why the generated waveforms become red, and all values appear 'U'? Is there any declaration missed? Thanks
  9. S

    how to operate ADC08D1500

    I'm studying the operation of a new product ADC08D1500 Board, but how to download data from PC to the Board, into the part which is virtex4 FPGA block? Is there any concrete operational procedures? Thanks
  10. S

    How to download data from ADC08D1500 to FPGA?

    I'm studying the WaveVision4 System, of which the Evaluation Board is using ADC08D1500. Is it connected to Data Capture Board through Future Bus Connector (J4)? How to download data from ADC Evaluation Board to Data Capture Board (FPGA)?
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