question of testbench

[sally wang]

when write a testbench of VHDL, why the generated waveforms become red, and all values appear 'U'? Is there any declaration missed? Thanks

 

[A.Anand Srinivasan]

please post your program... the U denotes that your signal is undefined....

 

[sally wang]

I've already figured out the problem. It's bcoz I selected the vhdl file but not the test-bench file to generate behavioral model, so that it's undefined. Thank you for your concern!