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Recent content by sakthi_tallika

  1. sakthi_tallika

    how to use output of c program in my vhdl program

    there is a concept of FLI(Foriegn language interface) to link C model and vhdl model.
  2. sakthi_tallika

    How to use IP compile by vlog to do simulation in top level using ModelSIM?

    Re: Modelsim question you can use the following options. +libext+.v -y <your ip directory path>
  3. sakthi_tallika

    $system() in verilog HDL

    I hv checked this also before placing a querry. I am not seeing any PLI in my env. It is a pure verilog. I am not sure whether this new system task is added in v2k.
  4. sakthi_tallika

    $system() in verilog HDL

    Even I never used/heared about this task. But in one of our customer enviornment this task is used. Basically this task is used to execute OS command. In our env, we are using this command to get the system date(unix command "date"). regards, Sakthi.
  5. sakthi_tallika

    $system() in verilog HDL

    verilog system task run unix command Does anybody knows about the $system() system task in verilog? please let me know the list of arguments used in this task --sakthi
  6. sakthi_tallika

    analog design interview questions

    Re: job interview questions It depends on your requirement. for ex. if you want to detect a pattern and generate output while detecting the last bit of the particular pattern(no delay), mealy FSM will be more useful.
  7. sakthi_tallika

    How to take care of set up and hold violations in gated clocks & multi cycle designs?

    Re: Query multi cycle path information should be given by the RTL designer.
  8. sakthi_tallika

    Documents for learning SystemC

    systemc from the ground up 2009 systemverilog would be good & powerful. At the same time it is very costly. systemC is an open standard and we can use C++ compiler to achieve many things.
  9. sakthi_tallika

    rom interface in verilog

    I am not sure whether I understood your question correctly. Here is my view. If you don't want to use the TB to generate rom address, we can use 2bit counter in the top module. For every clock(or based on your control) the counter will be incremented by 1. So that you will get the following seq...
  10. sakthi_tallika

    Documents for learning SystemC

    learning system c Thanks a lot neo. I have downloaded that book.
  11. sakthi_tallika

    Documents for learning SystemC

    how to understand systemc testbench Thanks for your reply. When I tried to open the link you have provided, I got the following message. "it was removed".. Regards, Sakthi.
  12. sakthi_tallika

    Documents for learning SystemC

    systemc books download Yes. Ihave downloaded some zip file. I couldn't locate the correct file for all compilation & simulation related commands. Regards, Sakthi.
  13. sakthi_tallika

    About random data generation using verilog language

    If you want different seed need to be used, please try this. reg [31:0] data ; initial data = $random(); <your loop> data = $random(data) ; this logic will change your seed for each iteration. regards, sakthi.
  14. sakthi_tallika

    Documents for learning SystemC

    Hi, I am new to SystemC based verification/design. I am familiar with Vera/verilog/vhdl. I would like to learn SystemC in a systematic way. Is there any systemC methodology document like Vera rvm,Specman eRM? Please suggest some way to create a simple code and compile/simulate the code...
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