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Recent content by Sadegh.j

  1. Sadegh.j

    frequency divider in simulink

    Re: simulink divider sorry about the stupid question, but what is the name of the block that has a falling edge of the clock drawn on it?
  2. Sadegh.j

    Integer-N PLL simulation in Simulink

    Hi All I need to some how simulate the /N (frequency devider) in simulink, any ideas?
  3. Sadegh.j

    how to build a buffer with fixed delay with different VDD

    I agree, you have to some how eliminate the effect of VDD variation on the output, use a bandgap
  4. Sadegh.j

    Exporting data from Cadence to MATLAB

    JoannesPaulus: Thanks, not for the button, for the ocean script bit, what is the differencve between writing the script and simply pressing the button?
  5. Sadegh.j

    Exporting data from Cadence to MATLAB

    Do you have a manual for that?
  6. Sadegh.j

    Adding Legends in Cadence

    So it does not automatically do it, like matlab does, right?
  7. Sadegh.j

    Implementing a buffer using a basic op amp

    Hey You can do a few things, but the easiest is probably this one: https://upload.wikimedia.org/wikipedia/commons/thumb/6/68/Unity_gain_buffer_amp.svg/400px-Unity_gain_buffer_amp.svg.png If you want to design it in transistor level, you can use a source follower (common drain).
  8. Sadegh.j

    Adding Legends in Cadence

    Hi all I have a few plots in cadence and I want to add legends to them, how can I do this. Thanks a lot
  9. Sadegh.j

    Exporting data from Cadence to MATLAB

    Hi all I am writing a report, and I want to export the simulation data from cadence to MATLAB, and plot the data in MATLAB, since I will have more options for plotting in MATLAB. How can I do this? Thanks all
  10. Sadegh.j

    DC feedback in amplifier design

    Hi To design amplifier, one very useful method that I have come across is to use a DC feedback to fix the DC level of the output. Can some one elaborate on this? Thanks
  11. Sadegh.j

    PLL's jitter, stability, etc according to it's BW

    PLL BW, jitter etc Hi all What is the relation ship between the PLL BW and its 1) output jitter 2) lock time 3) Stability Thanks Any reference would be appreciated
  12. Sadegh.j

    Copy in Arrays in Cadence

    Perfect, Thanks
  13. Sadegh.j

    PLL maximum and minimum input reference frequency

    Hi yes, Imagine your frequency is 1GHz, your period would be 1ns and in 10ns, the input chances 10 times, giving the PD, lets say, 10 chances of fix the VCO frequency. Now increase your input frequency to 10 Ghz, your period is 100ps, and in 10ns, the input chances 100 times, giving the PD 100...
  14. Sadegh.j

    Copy in Arrays in Cadence

    Hi all How do you copy a piece of metal (for example) and paste 20 of it, equally spaced, like in an array in Cadence layout? Thanks
  15. Sadegh.j

    Layout technique explanation

    technique in doing a back layout About the symmetry, I can understand that the two inputs should basically "see" the same transistors and all, but what if you have several blocks? Is it enough to make each block symmetrical? Or should the whole thing also be symmetrical?
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