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Recent content by sachin_kirdat

  1. S

    calculating k-factor in .lib

    No you can not do that. It is your .lib is cherazed for 1.5v and 1.62v & not that your best/worst voltage depends on K factor. generally around 10% variation will be considered for charct lib with Typ voltage. Can change company to company or process to process. finding a K factor from .lib...
  2. S

    Doubt about de-asserting a reset and generating a peripheral clock

    generated clock reset think of start up time of oscillator Added after 15 seconds: jitter and unstable clk
  3. S

    what's the MC stands for ?

    whats an mc Is it all mask stram out or only matel revision stream out, in case of metal revision it may be mask check. what does they do they will X-or new layers with old one and provide results back to layout ebineer for review.
  4. S

    huge current problem by hsim

    For HSIM acuracy is very very sensitive, check following parameters in ur test bench. 3. Recomended HSIM parameters - .param HSIMOUTPUT=fsdb .param HSIMVDD= 2.5 $Lowest power supply .param HSIMOUTPUTFLUSH=2e-7 .param HSIMREDEFSUB=1 .param HSIMSPEED= 5 .param HSIMSPICE=1 .param...
  5. S

    Do we find timing issues(violations) in analog systems ??

    Re: Timing in analog ?? yes, Hspice/hsim can do it.
  6. S

    Do we find timing issues(violations) in analog systems ??

    Timing in analog ?? yes, it is called loading in analog as it is full coustem only and do not characterized like digital. to catch this you have to run simulations only at transister level. hope this help you
  7. S

    Why are pads used to connect chip to the I/O pins?

    necessity of pads you can not connect directly to IO, there are some DRC that you have to follow such for making connectiuon you need some large area where ur bond wire will be connected and some empty area around it. so take in as ... you can not connect it directly to core's IO you need some...
  8. S

    Post layout simulation

    Hi, Simulations PASSED and still you may see some signals are Z or X, as they are not beening used or not under test. Some thime that may be acceptable, where intenally upi have tri stated some signal through design or some signals are un initilized. but in some case that might be...
  9. S

    What to do when performance declines because of the temperature?

    performance problem this is something interesting you have any doc or any ref for this bellow 65nm for less temp more delays or for worst corner use lowest temp.
  10. S

    Why are pads used to connect chip to the I/O pins?

    necessity of pads you can say that this layer is kind of cover to ur silicon. and it will protect from dust partical
  11. S

    Why are pads used to connect chip to the I/O pins?

    necessity of pads you have to get a internal signal to the outside and you can do it with the help of pad ... now the question is why pad layer only ... why we can not bond directly to metal layer ? ans is we do not keep all layer exposed to atmosphire after manufacturing to aoide a relibility...
  12. S

    How a buffer improves the strength of the signal ?

    about Buffers.. typically bufer will improve rise and fall time, which is one ofthe decideing factor for delay of the next cells.
  13. S

    can i see the contents of .tch file without .ict file ??

    .tch file for qrc try out RCgen -ictout xxxx.tch
  14. S

    can i see the contents of .tch file without .ict file ??

    .tch file for qrc It is possible to generate ( recover) ICT file from .tch file. I do not rember exectly what was commend for that but it should be there in RCGen's command manual or you can ask for command to cadence support

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