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How to tell formality to match two points with different name?

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chc1625

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Hi,all

In the rtl, I define a two-dimension array like this: reg [15:0] ibuf0_rd[11:0]; . After dc synthesis, the register are changed name to ibuf0_rd_reg1511,ibuf0_rd_reg1510.... so the formality can not match the ibuf0_rd_reg[15][11] in ref and ibuf0_rd_reg1511 in netlist,
are there some command tell formality match them?

Thanks
 
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I don't remember the command, but yes, mapping commands exist in every formal verification tools. Check the manual.
 
I have fixed the problem. The reason is I forgot to read some svf file of the sub-module.
 

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