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Recent content by rvidya

  1. R

    Verilog module related doubt

    Sorry. I didn't get you.Could you explain it more?
  2. R

    Verilog module related doubt

    hi, In Verilog, suppose I have a module A inside which a smaller module B should be instantiated. Suppose in module B's code the first line is like : module B(o1,o2,i1,i2); where o1,o2 are outputs and i1,i2 are inputs of B. But suppose, while instantiation, A is not able to give both the...
  3. R

    LDO design procedure help

    Thanks a lot for the help..I jus got a copy of the book suggested...
  4. R

    Verilog DFF questions

    Tht purely depends on ur application... If the reset is edge triggered use negedge/posedge, else just reset/!reset...Normally for asynchronous resets, just reset is enough....
  5. R

    Verilog DFF questions

    1. ! 123 is 1'b0 whereas ~3'b101 is 3'b010. 2. Begin and end is for each if or else statement. Not for the if-else structure as a whole. If there are multiple statements under 'IF', use begin-end combination. If and else are to be treated as separate structures. always @ ( posedge clk or...
  6. R

    Verilog DFF questions

    ~ performs bitwise negation whereas ! is a logical operator. In this case both will give u the same result. Begin has to be used whenver there are multiple statements involved. For eg. if u had to assign values to multiple variables in the if statement u need to use begin. In this case u can...
  7. R

    LDO design procedure help

    Sorry...I didnt mean to use NMOS and PMOS together...I need to design an LDO with PMOS as pass transistor and another LDO with NMOS as pass transistor... - - - Updated - - - Sorry...I didnt mean to use NMOS and PMOS together...I need to design an LDO with PMOS as pass transistor and another...
  8. R

    LDO design procedure help

    Hi all... I'm trying to design an LDO with both NMOS and PMOS pass elements. Can anyone please suggest any link/ book which talks about the design procedure of the same? How to decide the gain of the error amplifier, pass transistor width etc.? Also for NMOS pass element, we'll need to use...
  9. R

    Wide swing folded cascode

    Thanks...,There was a mistake in my calculations... forgot to convert frequency into radians...problem solved now...
  10. R

    [SOLVED] watching slew rate in folded cascade simulation

    check up allen holdberg chapter 6 simulation and measurement of op amps.... To measure slew rate, connect the opamp in voltage follower config and measure the slope of the transient response for a capacitive load...
  11. R

    Wide swing folded cascode

    hi... I'm trying to design a wide swing folded cascode amplifier..I'm following the design procedure in Allen Holdberg...But I'm getting devices sizes with w/l <1 for some of the transistors..Is it valid? Or should I readjust the sizes by changing gm/id? Thanks in advance
  12. R

    How to Start to learn the Digital Electronics & Analog Design by own self at home.

    Re: How to Start to learn the Digital Electronics & Analog Design by own self at home As said earlier, it will be difficult task to be an expert in both...Digital is easier of the two...but analog poses challenges very interesting once we learn it...Read Microelectronic circuits by Sedra and...
  13. R

    How to increase the ICMR

    Also the design approach is given in Allen Holdberg chapter 6 cmos operational amplifiers...readjust device widths accordingly...

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