Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
PSPICE is a PC board level simulator that uses IBIS models. LTSPICE should also read IBIS models. So the spice deck should be compatible. I actually represent Legend Design (I founded EDATechForce which represents Legend Design), that makes an IBIS based simulator so I can find out for you...
Actually the debate was about Arnoldi delay calculator algorithm vs AWE (pre 1999). The algorithm is about Driver Network Reduction of mesh networks. When the far end of a net is dangling (no resistive load), the entire net resistance would fail to converge during model reduction (from complex...
It is clear from the replies here that many of you have not done a real chip design. You do need a "seed" sdc file which defines clocks and input/output delays for the synthesizer. It should also have false paths, multicycle paths, and generated clocks. After synthesis you generate a NEW sdc...
I was an RTL Compiler Core Comp Technical Leader at Cadence. The tool is NOT free. In fact, it is > $80,000. No freeware. If you want a free solution then expect poor results. Anyway, for RTL power you should use Sequence Design (now Apache) PowerTheater. Power at RTL will not be accurate...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
