Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by rp276

  1. R

    setup time and hold time

    If we have to calculate setup time, we don't consider clock period while in setup violation we use clock period.please explain...:?:
  2. R

    high pass filter using opamp

    if a capacior is inserted in the negative feedback in series with the resistance...how the highpass filter will behave. please explain?
  3. R

    difference between feature size and channel length in mosfet

    kindly explain..what is difference between feature size and channel length in mosfet????
  4. R

    and gate using pmos and nmos

    can we make" and gate "with only one pmos and only one nmos? please help...
  5. R

    What is the significance of switching threshold in cmos?

    what is the significance of switching threshold in cmos?? how it affects the circuit?? please help..
  6. R

    low pass and high pass filter design using opamp

    can we configure low pass and high pass filter as inverting configuration using opamp? why? why not? please help..
  7. R

    propagation delay in cmos

    how to calculate propagation delay in cmos?? how to calculate equivalent capacitance?
  8. R

    setup and hold time and causes

    please explain what is setup and hold time? what are its causes? and why it is so important??
  9. R

    velocity saturation in devices

    why velocity saturation occurs in short channel device and not in long channel device..????:?:

Part and Inventory Search

Back
Top