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Hi, and thank you for your quick reply!
When I insert Clock into sensitivity list, and create "clocked process" with
if(CLK'event and CLK = '1') then ...
Then those latches go away, but I would prefer not to have this. I plan to connect those two input signals to mechanical buttons on my...
Hi, I'm trying to build an PWM generator, and I plan to have 2 input signals (1 bit each), where one would increment duty factor, and another one would decrement it.
So, I have two signals, pulse length and pause length, and their sum will always be 100.
Signal definitions:
signal...
Hello, I'm trying to create a multiplier for real numbers (with fixed decimal point). So, let's assume I have two vectors, both 10 bits long. Form is like this> 1.3.6 (1 sign bit+3 integer value bits + 6 bits of behind decimal value).
Now, I expect output to be 20 bits long, of course. However...
Don't know really, I just thought maybe I would need it for something else, and I'm still learning, so I considered this project as an exercise. To be honest, I would never think of what you did here...
Thanks a lot for your comment, really helpful!
Hello and thank you for your fast reply. However, this doesn't solve my problem. You still have only one carry bit available, which is not enough. Not to mention you never use "c" vector.
EDIT: I believe I have found a solution.. Can anyone experienced and well versed please review and tell me...
I'm sorry but I don't see an option of edition first post, so I had to do a double post.
I have a new idea, can you please tell me if this makes sense and would it work?
So, there are 12 bit vectors, to classic addition (like presented above on first 11 bits (10 downto 0)), and then, we have 4...
Hello, I'm learning VHDL and currently trying to implement full adder that has three inputs (a, b, c), and carry_in as is required for this type of adder.
My idea was to implement regular full adder>
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC...
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