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HI
I wrote a vhdl memmory controller for my external cellram( all working fine)
Now i want to use this controller in a larger design and want to put this controller under another module !
Basicly i can do it with a regular inputs and outputs with a regular mapping,
from one componnet to another...
Hi
Thanks for your detailed response. Im new to fpga and will be glad if you can clearify on a few things.
1)whats an "undified signal??
2)I dont have asynchronous rests. But i would like to know how can it make the hardware not work?(my code is syntisised).
3)whats 'H' and 'L' ??
4)how can i...
What do i need to do if my project in the simulation is working flawlessly but when i try it on the board itself is giving me weired problems.
initialy i thoght maybe there is a problem with timing but i checked and everything seems fine.
(i have nexys 3 board).
I have a spartan 6 nexys 3 board with a vga conector i already wrote the code to display things on the screen and its working.
My question is more related to vga protocol.
In the vga conector there are 8 bits for color 3 for red ,3 for green and 2 for blue. making a total of 256 colors .
How...
Hi,
How can i change the amount of time the simulation is working then i launch it from ise(xilinx ise13.3.1).
I cant find it in prefernces? But i clearly remmber there was this option.
Currently its working 1000ns.( please dont tell me to hit run all or run for specified time thats not what i...
Hi
I just wrote some program in vhdl(using only behavioral code), i wanted that the program will work only in simulation.
But the funny thing that happened is that the code is synthesizeble without errors or warnings.
But than i simulate its not doing whats it's supposed to do.
after a few...
Its not working !:sad: ill post the full code maybe itll be easier to understand my problem.
entity bindiv is
Port ( mispar : in STD_LOGIC_VECTOR (4 downto 0);
mehalek : in STD_LOGIC_VECTOR (4 downto 0);
moza : out STD_LOGIC_VECTOR (4 downto 0);
reset: in...
mispar : in STD_LOGIC_VECTOR (4 downto 0); --defining 5 bit input
signal misparregi : std_logic_vector (8 downto 0) ; --defining 9 bit signal
i want to assighn the input "mispar" to the lowest bits in the signal "misparregi"
the compiler gives me an error telling me that they are diffrent...
Hi (English isn't my primary language so sorry for some grammar or Syntax mistakes)
I am new to fpga and vhdl, and have some confusion about some minor things.
I found a link to a sinewave generator vhdl code and explanation(i dont remmember the user who posted it BUT thank u verymuch!!!1)
Here...
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