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Hi,
Many years I used PCAD PCB design EDA in my work. I am not a critic of Altium corporate decision. But Altium leaves me (by the way - like as many other professionals) without any alternative. I decided to work with Mentor Expedition.
My question is - which PCB Translators are the best...
Friends,
Advice please.
PCI Express card get SSC 100 MHz clock and converts it into 125 low jitter clock.
Problem is schematic. Suggested component (by xilinx) has 6 LVDS outputs. Case TSSOP28.
I would want to use component with only 2 differential outputs. Pproblem. Present component...
DDR IP
Hi,
DDR IP, produced by Xilinx MIG placed some strange signals in the *.usf.
For example: READ_EN_IN or READ_EN_OUT or PASS.
Anybody knows what is it?
Roman
Re: RJ48 and RJ45
Ok, Tnk$. If so, what pinout should be choosed for E1/T1 in the case of RJ-48 using.
And may be you know, which standards determines this issue.
What do you neen by cost effective way. NRE ?
The most effective design solution may be using of PCI Express bridge. Try to find such component first. It can be PLX , AMCC or others PCI VLSI vendors.
Less effective way is to aquare IP core for Xilinx or Altera FPGA
t1/e1 impedance
Hi,
Please advice, how should look the system with Quad Falc and 2 work modes.
One mode is the normal E1/T1 interface with corresponding E1/T1 impedances.
Second mode base on disconnection of E1/T1 Falc periferals and connection of high impedance front end.
Thank you
Re: mpc82xx to TMS641x
As I said, I worked with C6203 with Expansion bus. Yes some control signal like XCS routed through PLD. 32 bit Local bus interfaces to Expansion bus through buffer.
Roman
P.S. Try to find AN on this topic on TI web.
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