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Recent content by Romanp

  1. Romanp

    Converting user layer to board outline

    Please, suggest how to convert any grafics presented on some user layer to the board (or route) outline? Sorry, I talk about Mentor Expedition
  2. Romanp

    import DXF file into Expedition

    Hi, How to convert user layer to board outline?
  3. Romanp

    PCB TRANSLATORS - REVIEW OF THE BEST S/W

    Hi, Many years I used PCAD PCB design EDA in my work. I am not a critic of Altium corporate decision. But Altium leaves me (by the way - like as many other professionals) without any alternative. I decided to work with Mentor Expedition. My question is - which PCB Translators are the best...
  4. Romanp

    Jitter attenuator with HCSL output

    Friends, Advice please. PCI Express card get SSC 100 MHz clock and converts it into 125 low jitter clock. Problem is schematic. Suggested component (by xilinx) has 6 LVDS outputs. Case TSSOP28. I would want to use component with only 2 differential outputs. Pproblem. Present component...
  5. Romanp

    Strange signals in DDR IP, i.e. READ_EN_IN or READ_EN_OUT

    DDR IP Hi, DDR IP, produced by Xilinx MIG placed some strange signals in the *.usf. For example: READ_EN_IN or READ_EN_OUT or PASS. Anybody knows what is it? Roman
  6. Romanp

    ORCAD NEW PART Generatin From Xilinx pkg. files

    How to create new Oracd component from Xilinx package ASCII files?
  7. Romanp

    What are the differences between RJ48 and RJ45?

    Re: RJ48 and RJ45 Ok, Tnk$. If so, what pinout should be choosed for E1/T1 in the case of RJ-48 using. And may be you know, which standards determines this issue.
  8. Romanp

    What are the differences between RJ48 and RJ45?

    What differents RJ45 from RJ48?
  9. Romanp

    PCI Express card design. How?

    What do you neen by cost effective way. NRE ? The most effective design solution may be using of PCI Express bridge. Try to find such component first. It can be PLX , AMCC or others PCI VLSI vendors. Less effective way is to aquare IP core for Xilinx or Altera FPGA
  10. Romanp

    E1/T1 High Impedance Front End

    No, I ment something other. I need to hear E1/T1 signaling without affecting on its amplitude and friquency parameters.
  11. Romanp

    E1/T1 High Impedance Front End

    t1/e1 impedance Hi, Please advice, how should look the system with Quad Falc and 2 work modes. One mode is the normal E1/T1 interface with corresponding E1/T1 impedances. Second mode base on disconnection of E1/T1 Falc periferals and connection of high impedance front end. Thank you
  12. Romanp

    PMC Carrier: extending slots of a VME Single Board Computer

    Re: PMC Carrier What do you meen by PMC-PCI Mezzanine Card, is not it Roman
  13. Romanp

    PCI Expansion +Vi/o in Universal board

    Hi, Advice please, how to include valuable(+5 V or +3V3) +Vi/o in the universal PCI expancion board into the board 3v3 power.
  14. Romanp

    Xilinx EPLD XL9572 GTS AND GCK INPUTS

    xilinx epld Hi, Can I use GTS and GCK inputs of xilinx XL95xx EPLD family as GPIO (Inputs and Outputs).
  15. Romanp

    Interface between mpc82xx and Texas DSP 6416 HPI

    Re: mpc82xx to TMS641x As I said, I worked with C6203 with Expansion bus. Yes some control signal like XCS routed through PLD. 32 bit Local bus interfaces to Expansion bus through buffer. Roman P.S. Try to find AN on this topic on TI web.

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