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During my W/L sizing in schematic design while using TSMC 45nm technology, I faced this issue of finger spacing. I did before also, but I never noticed this error. My MOSFET width size is 60. As I cannot set the MOSFET width more than 1.5um in this schematic design, so I prefer 1.5um as each...
Thank You Tony for your answer. I understood in a broader point of view. Could you answer in a specific manner for sub-180nm process meaning? Does it mean lower technology of 180nm or something else, I am confused in that perspective. Thank you.
I am designing a oscillator circuit. I run it for DC node voltages and surprisingly I got different node voltages at output clock port for a group of corners. Is it normal or something wrong in my circuit design? (Simulation done in IC6 version cadence spectre)
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