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I am designing a oscillator circuit. I run it for DC node voltages and surprisingly I got different node voltages at output clock port for a group of corners. Is it normal or something wrong in my circuit design? (Simulation done in IC6 version cadence spectre)
This is normal.
An oscillator is a circuit in feedback. And the feedback is not a negative feedback to have a properly defined operating point.
During the DC simulation, which is basically KVL/KCL, the software you are using would arrive at some solution depending on the error tolerances that have been set. And these solutions can be different depending on the variables (corners, etc).
Technically, a DC simulation does not mean anything for an oscillator circuit since there is no DC steady state.
There are other simulation methods to get a periodic steady state solution from an oscillating circuit, (In cadence viz. PSS, PAC, etc)
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