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Recent content by rocking_vlsi

  1. R

    Difference between lint and spyglass

    Hi dpaul Why spyglass is best tool for linting, does it catch some issues which other tool cant?
  2. R

    Multi Voltage Design for low power

    How to partition design for multi-VDD low power?
  3. R

    gvim color scheme for verilog coding

    **broken link removed** Desert colr scheme is good. You can turn on syntax. N lot more options in above link. Posted via Topify on Android
  4. R

    how efuse memory works?

    How efuse memory works? What kind circuitry used for each cell?
  5. R

    Important RTL lint errors

    Hi What are important lint errors that are needs be fixed before taking RTL for synthesis ?
  6. R

    setup hold and transition

    To work chip properly both violations needs to be fixed. Only thing is if you have setup violation chip will still work properly at lower frequency which not same in case of hold violation. Posted via Topify on Android
  7. R

    How do we define clock domain

    Thanks for reply. Then 100Mhz and 150Mhz are not synchronous right? Posted via Topify on Android
  8. R

    How do we define clock domain

    How do we define a clock domain? Can 50Mhz and 150Mhz could be synchronous? Posted via Topify on Android
  9. R

    recommend books for asic implementation of video & audio processing

    Hi Please suggest me books which has implementation(ASIC or FPGA) methodologies for basic DSP and information theory designs.
  10. R

    check_tluplus - error

    How to solve mapping errors in Design compiler synthesis --------- Sanity Check on TLUPlus Files ------------- Info: Found HALF_NODE_SCALE_FACTOR 0.900000 in TLUPlus files. 1. Checking the conducting layer names in ITF and mapping file ... Error: Layer "M1" (metal1) exists in the MW-tech but...
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    Library preparation for Design Compiler in topo mode

    What will be mw_reference_library in create_mw_lib ?
  12. R

    Library preparation for Design Compiler in topo mode

    Hi I want to run Design compiler in topo mode. 1) my first question is how to create milyway reference design? 2) what are the types files, that we can give physical information of cells to design compiler? 3) i have tf file, itf file, lef file, gds fle, mw/target_librayr/CELL...
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    Data mux for clock domain crossing

    http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf In Atrenta spyglass documents, you will get more details about synchronizer structures. Even mentor Questa CDC user guide has this information.
  14. R

    Efficient way of adding 8 x8 matrx elements

    Hi What is optimal way of adding 8 x8 matrix elements? Can you suggest time based and area based approaches?
  15. R

    meaning of post synthesis simulation

    There are two reasons for post synthesis simulation 1) Synthesis and simulation mismatch : Your synthesized netlist might not behave functionally as expected. 2) Timing simulation : https://digitalelectronics.blogspot.in/2006/10/gate-level-simulation-introduction.html
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