Multi Voltage Design for low power

[rocking_vlsi]

How to partition design for multi-VDD low power?

 

[artmalik]

It is supported by most tools with multi-voltage domains defined at the PD level.At the RTL level this has less usage because most of the people "don't" want to touch RTL. After placement, the voltage domains are defined using the CPF format. This way the various timing is done, constraints are written and also design tools add the isolation gates/level shifters etc. there is now more effort made to introduce Multi-mode multi corner analysis at synthesis level itself because timing is impacted by voltage level of operations. the flow is kind of getting there. CPF/UPF flow is needed for the multi-VDD power. This book gives an overall picture
https://www.amazon.com/Power-Method...d=1417566077&sr=8-8&keywords=low+power+design